Texas Instruments TMS320C6747 DSP HC Operating Mode Register HCCONTROL Field Descriptions, Value

Registers			www.ti.com
		Table 3. HC Operating Mode Register (HCCONTROL) Field Descriptions
Bit	Field	Value	Description
31-11	Reserved	0	Reserved
10	RWE	0-1	Remote wake-up enable.
9	RWC	0-1	Remote wake-up connected.
8	IR	0	Interrupt routing. The USB host controller does not provide an SMI interrupt. This bit must be 0 to allow
			the USB host controller interrupt to propagate to the MPU level 2 interrupt controller.
7-6	HCFS	0-3h	Host controller functional state. A transition to USB operational causes SOF generation to begin in 1
			ms. The USB host controller can automatically transition from USB suspend to USB resume, if a
			downstream resume is received. The USB host controller enters USB suspend after a software reset.
			The USB host controller enters USB reset after a hardware reset. The USB reset state resets the root
			hub and causes downstream signaling of USB reset.
		0	USB reset
		1h	USB resume
		2h	USB operational
		3h	USB suspend
5	BLE		Bulk list enable.

0The bulk ED list is not processed in the next 1 ms frame. The host controller driver can modify the bulk ED list. If the driver removes the ED pointed to by the HC current bulk register (HCBULKCURRENTED) from the ED list, it must update HCBULKCURRENTED to point to a current ED before it reenables the bulk list.

1Enables processing of the bulk ED list. The HC head bulk register (HCBULKHEADED) must be 0 or point to a valid ED before setting this bit. The HC current bulk register (HCBULKCURRENTED) must be 0 or point to a valid ED before setting this bit.

4 CLE Control list enable.

0The control ED list is not processed in the next 1 ms frame. The host controller driver can modify the control ED list. If the driver removes the ED pointed to by the HC current control register (HCCONTROLCURRENTED) from the ED list, it must update HCCONTROLCURRENTED to point to a current ED before it reenables the control list.

1Enables processing of the control ED list. The HC head control register (HCCONTROLHEADED) must be 0 or point to a valid ED before setting this bit. The HC current control register (HCCONTROLCURRENTED) must be 0 or point to a valid ED before setting this bit.

3	IE		Isochronous enable.
		0	Isochronous EDs are not processed. The USB host controller checks this bit every time it finds an
			isochronous ED in the periodic list.
		1	Enables processing of isochronous EDs in the next frame, if not in the current frame.
2	PLE		Periodic list enable.
		0	Periodic ED lists are not processed. Periodic list processing is disabled beginning with the next frame.
		1	Enables processing of the periodic ED lists. Periodic list processing begins in the next frame.
1-0	CBSR	0-3h	Control/bulk service ratio. Specifies the ratio between control and bulk EDs processed in a frame.
		0	1 control ED per bulk ED.
		1h	2 control EDs per bulk ED.
		2h	3 control EDs per bulk ED.
		3h	4 control EDs per bulk ED.

14 Universal Serial Bus OHCI Host Controller SPRUFM8–September 2008

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