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TMS320C6747 DSP manual SPRUFM8-September, Submit Documentation Feedback
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TMS320C6747 DSP
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Specifications
2.1 USB1 Module Clock and Reset
HC Command and Status Register HCCOMMANDSTATUS
Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set the
HC Interrupt Enable Register HCINTERRUPTENABLE
USB Host Controller Access to System Memory
HC Operating Mode Register HCCONTROL
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SPRUFM8–September
2008
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Contents
Users Guide
TMS320C6747 DSP Universal Serial Bus USB OHCI Host Controller
SPRUFM8-September
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Contents
List of Figures
HC HCAA Address Register HCHCCA Field Descriptions
List of Tables
USB Host Controller Registers
About This Manual
Read This First
Preface
Notational Conventions
1 Introduction
Universal Serial Bus OHCI Host Controller
Users Guide
1.1 Purpose of the Peripheral
2 Architecture
2.1 USB1 Module Clock and Reset
2.1.2 USB1 Module Local Bus Clock and Local Reset
2.1.1 Internal System Bus Clocks Needed by the USB1 Module
2.3.2 Overcurrent Protection Input Pins Not Supported
2.3 USB1 Module Differences From OHCI Specification for USB
2.3.1 Power Switching Output Pins Not Supported
2.2 USB1 Module Open Host Controller Interface Functionality
2.4.2 OHCI USB Suspend State
2.4 Implementation of OHCI Specification for USB
2.4.1 USB Host Controller Endpoint Descriptor ED List Head Pointers
2.7 Physical Addressing
2.6 USB Host Controller Access to System Memory
2.5 OHCI Interrupts
Figure 1. Relationships Between Virtual Address Physical Address
3 Registers
Table 1. USB Host Controller Registers
3.1 OHCI Revision Number Register HCREVISION
3.2 HC Operating Mode Register HCCONTROL
Figure 3. HC Operating Mode Register HCCONTROL
Figure 2. OHCI Revision Number Register HCREVISION
Value
Table 3. HC Operating Mode Register HCCONTROL Field Descriptions
Field
Description
Field
3.3 HC Command and Status Register HCCOMMANDSTATUS
Figure 4. HC Command and Status Register HCCOMMANDSTATUS
Value
Registers
3.4 HC Interrupt and Status Register HCINTERRUPTSTATUS
Figure 5. HC Interrupt and Status Register HCINTERRUPTSTATUS
Field
Field
3.5 HC Interrupt Enable Register HCINTERRUPTENABLE
Figure 6. HC Interrupt Enable Register HCINTERRUPTENABLE
Value Description
Registers
3.6 HC Interrupt Disable Register HCINTERRUPTDISABLE
Figure 7. HC Interrupt Disable Register HCINTERRUPTDISABLE
Field
Figure 8. HC HCAA Address Register HCHCCA
3.7 HC HCAA Address Register HCHCCA
3.8 HC Current Periodic Register HCPERIODCURRENTED
Table 8. HC HCAA Address Register HCHCCA Field Descriptions
Table 10. HC Head Control Register HCCONTROLHEADED Field Descriptions
3.9 HC Head Control Register HCCONTROLHEADED
Figure 10. HC Head Control Register HCCONTROLHEADED
Registers
Field
3.10 HC Current Control Register HCCONTROLCURRENTED
Figure 11. HC Current Control Register HCCONTROLCURRENTED
Description
Figure 12. HC Head Bulk Register HCBULKHEADED
3.11 HC Head Bulk Register HCBULKHEADED
3.12 HC Current Bulk Register HCBULKCURRENTED
Table 12. HC Head Bulk Register HCBULKHEADED Field Descriptions
Figure 14. HC Head Done Register HCDONEHEAD
3.13 HC Head Done Register HCDONEHEAD
3.14 HC Frame Interval Register HCFMINTERVAL
Table 14. HC Head Done Register HCDONEHEAD Field Descriptions
Figure 16. HC Frame Remaining Register HCFMREMAINING
3.15 HC Frame Remaining Register HCFMREMAINING
3.16 HC Frame Number Register HCFMNUMBER
Figure 17. HC Frame Number Register HCFMNUMBER
Field
3.17 HC Periodic Start Register HCPERIODICSTART
Figure 18. HC Periodic Start Register HCPERIODICSTART
Value
Registers
3.18 HC Low-Speed Threshold Register HCLSTHRESHOLD
Figure 19. HC Low-Speed Threshold Register HCLSTHRESHOLD
Field
Table 20. HC Root Hub A Register HCRHDESCRIPTORA Field Descriptions
3.19 HC Root Hub A Register HCRHDESCRIPTORA
Figure 20. HC Root Hub A Register HCRHDESCRIPTORA
Field
Table 21. HC Root Hub B Register HCRHDESCRIPTORB Field Descriptions
3.20 HC Root Hub B Register HCRHDESCRIPTORB
Figure 21. HC Root Hub B Register HCRHDESCRIPTORB
Registers
Table 22. HC Root Hub Status Register HCRHSTATUS Field Descriptions
3.21 HC Root Hub Status Register HCRHSTATUS
Figure 22. HC Root Hub Status Register HCRHSTATUS
Field
Registers
3.22 HC Port 1 Status and Control Register HCRHPORTSTATUS1
Figure 23. HC Port 1 Status and Control Register HCRHPORTSTATUS1
Field
Description
Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set the
Field
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Registers
3.23 HC Port 2 Status and Control Register HCRHPORTSTATUS2
Figure 24. HC Port 2 Status and Control Register HCRHPORTSTATUS2
Field
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Field
Description
Applications
IMPORTANT NOTICE
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