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Texas Instruments TMS320C6747 DSP OHCI Interrupts, USB Host Controller Access to System Memory

Models: TMS320C6747 DSP

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2.5OHCI Interrupts

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Architecture

2.5OHCI Interrupts

The USB1 host controller can be controlled either by the ARM or the DSP. It has the ability to interrupt either processor.

2.6USB Host Controller Access to System Memory

The USB1 module needs to access system memory to read and write the OHCI data structures and data buffers associated with USB traffic. The switch fabric allows the USB host controller to access system memory, as shown in .

2.7Physical Addressing

Transactions on the internal bus use physical addresses, so all system memory accesses initiated by the USB host controller must use physical addresses. The ARM CPU can be configured to use virtual addressing. In this case, ARM side software manipulates virtual addresses that may or may not be identical to physical addresses. When virtual addressing is used, system software must perform the appropriate virtual address to physical address and physical address to virtual address conversions when manipulating the USB host controllers data structures and pointers to those data structures.

Figure 1 shows the ARM virtual address to physical address conversion.

Figure 1. Relationships Between Virtual Address Physical Address

00000000h

Processor

MMU

FFFFFFFFh

Processor	Processor
physical	virtual
address	address

SPRUFM8–September 2008

Universal Serial Bus OHCI Host Controller

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Texas Instruments TMS320C6747 DSP manual OHCI Interrupts, USB Host Controller Access to System Memory, Physical Addressing

Contents

TMS320C6747 DSP Universal Serial Bus USB OHCI Host Controller Users GuideSubmit Documentation Feedback SPRUFM8-SeptemberContents List of Figures HC HCAA Address Register HCHCCA Field Descriptions List of TablesUSB Host Controller Registers Notational Conventions Read This FirstPreface About This Manual1.1 Purpose of the Peripheral Universal Serial Bus OHCI Host ControllerUsers Guide 1 Introduction2.1.1 Internal System Bus Clocks Needed by the USB1 Module 2.1 USB1 Module Clock and Reset2.1.2 USB1 Module Local Bus Clock and Local Reset 2 Architecture2.2 USB1 Module Open Host Controller Interface Functionality 2.3 USB1 Module Differences From OHCI Specification for USB2.3.1 Power Switching Output Pins Not Supported 2.3.2 Overcurrent Protection Input Pins Not Supported2.4.2 OHCI USB Suspend State 2.4 Implementation of OHCI Specification for USB2.4.1 USB Host Controller Endpoint Descriptor ED List Head Pointers Figure 1. Relationships Between Virtual Address Physical Address 2.6 USB Host Controller Access to System Memory2.5 OHCI Interrupts 2.7 Physical AddressingTable 1. USB Host Controller Registers 3 RegistersFigure 2. OHCI Revision Number Register HCREVISION 3.2 HC Operating Mode Register HCCONTROLFigure 3. HC Operating Mode Register HCCONTROL 3.1 OHCI Revision Number Register HCREVISIONDescription Table 3. HC Operating Mode Register HCCONTROL Field DescriptionsField ValueValue 3.3 HC Command and Status Register HCCOMMANDSTATUSFigure 4. HC Command and Status Register HCCOMMANDSTATUS FieldField 3.4 HC Interrupt and Status Register HCINTERRUPTSTATUSFigure 5. HC Interrupt and Status Register HCINTERRUPTSTATUS RegistersValue Description 3.5 HC Interrupt Enable Register HCINTERRUPTENABLEFigure 6. HC Interrupt Enable Register HCINTERRUPTENABLE FieldField 3.6 HC Interrupt Disable Register HCINTERRUPTDISABLEFigure 7. HC Interrupt Disable Register HCINTERRUPTDISABLE RegistersTable 8. HC HCAA Address Register HCHCCA Field Descriptions 3.7 HC HCAA Address Register HCHCCA3.8 HC Current Periodic Register HCPERIODCURRENTED Figure 8. HC HCAA Address Register HCHCCARegisters 3.9 HC Head Control Register HCCONTROLHEADEDFigure 10. HC Head Control Register HCCONTROLHEADED Table 10. HC Head Control Register HCCONTROLHEADED Field DescriptionsDescription 3.10 HC Current Control Register HCCONTROLCURRENTEDFigure 11. HC Current Control Register HCCONTROLCURRENTED FieldTable 12. HC Head Bulk Register HCBULKHEADED Field Descriptions 3.11 HC Head Bulk Register HCBULKHEADED3.12 HC Current Bulk Register HCBULKCURRENTED Figure 12. HC Head Bulk Register HCBULKHEADEDTable 14. HC Head Done Register HCDONEHEAD Field Descriptions 3.13 HC Head Done Register HCDONEHEAD3.14 HC Frame Interval Register HCFMINTERVAL Figure 14. HC Head Done Register HCDONEHEADFigure 17. HC Frame Number Register HCFMNUMBER 3.15 HC Frame Remaining Register HCFMREMAINING3.16 HC Frame Number Register HCFMNUMBER Figure 16. HC Frame Remaining Register HCFMREMAININGValue 3.17 HC Periodic Start Register HCPERIODICSTARTFigure 18. HC Periodic Start Register HCPERIODICSTART FieldField 3.18 HC Low-Speed Threshold Register HCLSTHRESHOLDFigure 19. HC Low-Speed Threshold Register HCLSTHRESHOLD RegistersField 3.19 HC Root Hub A Register HCRHDESCRIPTORAFigure 20. HC Root Hub A Register HCRHDESCRIPTORA Table 20. HC Root Hub A Register HCRHDESCRIPTORA Field DescriptionsRegisters 3.20 HC Root Hub B Register HCRHDESCRIPTORBFigure 21. HC Root Hub B Register HCRHDESCRIPTORB Table 21. HC Root Hub B Register HCRHDESCRIPTORB Field DescriptionsField 3.21 HC Root Hub Status Register HCRHSTATUSFigure 22. HC Root Hub Status Register HCRHSTATUS Table 22. HC Root Hub Status Register HCRHSTATUS Field DescriptionsField 3.22 HC Port 1 Status and Control Register HCRHPORTSTATUS1Figure 23. HC Port 1 Status and Control Register HCRHPORTSTATUS1 RegistersSubmit Documentation Feedback Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set theField DescriptionField 3.23 HC Port 2 Status and Control Register HCRHPORTSTATUS2Figure 24. HC Port 2 Status and Control Register HCRHPORTSTATUS2 RegistersSubmit Documentation Feedback FieldDescription Applications IMPORTANT NOTICEProducts