Ohci Interrupts, Mmu | Texas Instruments TMS320C6747 DSP instruction

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Architecture

2.5OHCI Interrupts

The USB1 host controller can be controlled either by the ARM or the DSP. It has the ability to interrupt either processor.

2.6USB Host Controller Access to System Memory

The USB1 module needs to access system memory to read and write the OHCI data structures and data buffers associated with USB traffic. The switch fabric allows the USB host controller to access system memory, as shown in .

2.7Physical Addressing

Transactions on the internal bus use physical addresses, so all system memory accesses initiated by the USB host controller must use physical addresses. The ARM CPU can be configured to use virtual addressing. In this case, ARM side software manipulates virtual addresses that may or may not be identical to physical addresses. When virtual addressing is used, system software must perform the appropriate virtual address to physical address and physical address to virtual address conversions when manipulating the USB host controllers data structures and pointers to those data structures.

Figure 1 shows the ARM virtual address to physical address conversion.

Figure 1. Relationships Between Virtual Address Physical Address

00000000h

Processor

MMU

FFFFFFFFh

Processor	Processor
physical	virtual
address	address

SPRUFM8–September 2008

Universal Serial Bus OHCI Host Controller

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Texas Instruments TMS320C6747 DSP Ohci Interrupts, USB Host Controller Access to System Memory, Physical Addressing, Mmu

Contents

Literature Number SPRUFM8 September Users Guide SPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller 3 USB1 Module Bus 48-MHz Reference Clock USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset Internal System Bus Clocks Needed by the USB1 Module USB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USB Ohci USB Suspend State Implementation of Ohci Specification for USB MMU USB Host Controller Access to System MemoryOhci Interrupts Physical Addressing USB Host Controller Registers REV HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Ohci Revision Number Register Hcrevision Field Descriptions Control EDs per bulk ED Control list enablePeriodic list enable Control ED per bulk ED OCR HC Command and Status Register HccommandstatusSOC OCR BLF CLF HCR Rhsc HC Interrupt and Status Register HcinterruptstatusRhsc FNO WDH MIE HC Interrupt Enable Register Hcinterruptenable HC Interrupt Disable Register Hcinterruptdisable Hcca HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register Hchcca Field Descriptions Ched HC Head Control Register HccontrolheadedHC Head Control Register Hccontrolheaded Field Descriptions Controller HC Current Control Register HccontrolcurrentedCced HC Current Bulk Register Hcbulkcurrented Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Head Bulk Register Hcbulkheaded Field Descriptions HC Frame Interval Register Hcfminterval Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Head Done Register Hcdonehead Field Descriptions FRT HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber HC Frame Number Register Hcfmnumber Field Descriptions HC Periodic Start Register Hcperiodicstart HC Periodic Start Register Hcperiodicstart Reserved 13-0 HC Low-Speed Threshold Register HclsthresholdLST 628h Nocp Ocpm NPS PSM NDP HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions Potpg PPCM3 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3 PPCM2 PPCM1 PPCM0 HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register Hcrhstatus HC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2 Write of 1 to this bit clears the port 2 port enable bit When read as 0, USB reset is not being sent to portBegin signaling USB reset to port End of the USB reset sequence Rfid DSP