Ched | Texas Instruments TMS320C6747 DSP manual

Registers

www.ti.com

3.9HC Head Control Register (HCCONTROLHEADED)

The HC head control register (HCCONTROLHEADED) defines the physical address of the head endpoint descriptor (ED) on the control ED list. HCCONTROLHEADED is shown in Figure 10 and described in Table 10.

Figure 10. HC Head Control Register (HCCONTROLHEADED)

31			16
	CHED
	R/W-0
15	4	3	0
CHED			Reserved
R/W-0			R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 10. HC Head Control Register (HCCONTROLHEADED) Field Descriptions

Bit	Field	Value	Description
31-4	CHED	0-FFF FFFFh	Physical address of the head ED on the control ED list. This field represents bits 31-4 of the
			physical address of the head ED on the control ED list. EDs are assumed to begin on a 16-byte
			aligned address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
			addresses, see Section 2.7.
3-0	Reserved	0	Reserved

20

Universal Serial Bus OHCI Host Controller

SPRUFM8–September 2008

Submit Documentation Feedback

Image 20

Texas Instruments TMS320C6747 DSP manual HC Head Control Register Hccontrolheaded, Ched

Contents

Users Guide Literature Number SPRUFM8 September SPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the Peripheral USB1 Module Clock and Reset 2 USB1 Module Local Bus Clock and Local ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference Clock USB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface Functionality Implementation of Ohci Specification for USB Ohci USB Suspend State USB Host Controller Access to System Memory Ohci InterruptsPhysical Addressing MMU USB Host Controller Registers HC Operating Mode Register Hccontrol Ohci Revision Number Register HcrevisionOhci Revision Number Register Hcrevision Field Descriptions REV Control list enable Periodic list enableControl ED per bulk ED Control EDs per bulk ED HC Command and Status Register Hccommandstatus SOCOCR BLF CLF HCR OCR Rhsc HC Interrupt and Status Register HcinterruptstatusRhsc FNO WDH HC Interrupt Enable Register Hcinterruptenable MIE HC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca HC Current Periodic Register HcperiodcurrentedHC Hcaa Address Register Hchcca Field Descriptions Hcca Ched HC Head Control Register HccontrolheadedHC Head Control Register Hccontrolheaded Field Descriptions Controller HC Current Control Register HccontrolcurrentedCced HC Head Bulk Register Hcbulkheaded HC Current Bulk Register HcbulkcurrentedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field Descriptions HC Head Done Register Hcdonehead HC Frame Interval Register HcfmintervalHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field Descriptions HC Frame Remaining Register Hcfmremaining HC Frame Number Register HcfmnumberHC Frame Number Register Hcfmnumber Field Descriptions FRT HC Periodic Start Register Hcperiodicstart HC Periodic Start Register Hcperiodicstart HC Low-Speed Threshold Register Hclsthreshold LST628h Reserved 13-0 HC Root Hub a Register Hcrhdescriptora HC Root Hub a Register Hcrhdescriptora Field DescriptionsPotpg Nocp Ocpm NPS PSM NDP HC Root Hub B Register Hcrhdescriptorb HC Root Hub B Register Hcrhdescriptorb Field DescriptionsPPCM3 PPCM2 PPCM1 PPCM0 PPCM3 HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field Descriptions HC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changed When read as 0, USB reset is not being sent to port Begin signaling USB reset to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bit DSP Rfid