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Texas Instruments TMS320C6747 DSP HC Head Control Register HCCONTROLHEADED, Registers, Field

Models: TMS320C6747 DSP

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3.9HC Head Control Register (HCCONTROLHEADED)

Registers

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3.9HC Head Control Register (HCCONTROLHEADED)

The HC head control register (HCCONTROLHEADED) defines the physical address of the head endpoint descriptor (ED) on the control ED list. HCCONTROLHEADED is shown in Figure 10 and described in Table 10.

Figure 10. HC Head Control Register (HCCONTROLHEADED)

31			16
	CHED
	R/W-0
15	4	3	0
CHED			Reserved
R/W-0			R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 10. HC Head Control Register (HCCONTROLHEADED) Field Descriptions

Bit	Field	Value	Description
31-4	CHED	0-FFF FFFFh	Physical address of the head ED on the control ED list. This field represents bits 31-4 of the
			physical address of the head ED on the control ED list. EDs are assumed to begin on a 16-byte
			aligned address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
			addresses, see Section 2.7.
3-0	Reserved	0	Reserved

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Universal Serial Bus OHCI Host Controller

SPRUFM8–September 2008

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Texas Instruments TMS320C6747 DSP manual HC Head Control Register HCCONTROLHEADED, Registers, Field, Description

Contents

Users Guide TMS320C6747 DSP Universal Serial Bus USB OHCI Host ControllerSPRUFM8-September Submit Documentation FeedbackContents List of Figures HC HCAA Address Register HCHCCA Field Descriptions List of TablesUSB Host Controller Registers Read This First PrefaceAbout This Manual Notational ConventionsUniversal Serial Bus OHCI Host Controller Users Guide1 Introduction 1.1 Purpose of the Peripheral2.1 USB1 Module Clock and Reset 2.1.2 USB1 Module Local Bus Clock and Local Reset2 Architecture 2.1.1 Internal System Bus Clocks Needed by the USB1 Module2.3 USB1 Module Differences From OHCI Specification for USB 2.3.1 Power Switching Output Pins Not Supported2.3.2 Overcurrent Protection Input Pins Not Supported 2.2 USB1 Module Open Host Controller Interface Functionality2.4.2 OHCI USB Suspend State 2.4 Implementation of OHCI Specification for USB2.4.1 USB Host Controller Endpoint Descriptor ED List Head Pointers 2.6 USB Host Controller Access to System Memory 2.5 OHCI Interrupts2.7 Physical Addressing Figure 1. Relationships Between Virtual Address Physical Address3 Registers Table 1. USB Host Controller Registers3.2 HC Operating Mode Register HCCONTROL Figure 3. HC Operating Mode Register HCCONTROL3.1 OHCI Revision Number Register HCREVISION Figure 2. OHCI Revision Number Register HCREVISIONTable 3. HC Operating Mode Register HCCONTROL Field Descriptions FieldValue Description3.3 HC Command and Status Register HCCOMMANDSTATUS Figure 4. HC Command and Status Register HCCOMMANDSTATUSField Value3.4 HC Interrupt and Status Register HCINTERRUPTSTATUS Figure 5. HC Interrupt and Status Register HCINTERRUPTSTATUSRegisters Field3.5 HC Interrupt Enable Register HCINTERRUPTENABLE Figure 6. HC Interrupt Enable Register HCINTERRUPTENABLEField Value Description3.6 HC Interrupt Disable Register HCINTERRUPTDISABLE Figure 7. HC Interrupt Disable Register HCINTERRUPTDISABLERegisters Field3.7 HC HCAA Address Register HCHCCA 3.8 HC Current Periodic Register HCPERIODCURRENTEDFigure 8. HC HCAA Address Register HCHCCA Table 8. HC HCAA Address Register HCHCCA Field Descriptions3.9 HC Head Control Register HCCONTROLHEADED Figure 10. HC Head Control Register HCCONTROLHEADEDTable 10. HC Head Control Register HCCONTROLHEADED Field Descriptions Registers3.10 HC Current Control Register HCCONTROLCURRENTED Figure 11. HC Current Control Register HCCONTROLCURRENTEDField Description3.11 HC Head Bulk Register HCBULKHEADED 3.12 HC Current Bulk Register HCBULKCURRENTEDFigure 12. HC Head Bulk Register HCBULKHEADED Table 12. HC Head Bulk Register HCBULKHEADED Field Descriptions3.13 HC Head Done Register HCDONEHEAD 3.14 HC Frame Interval Register HCFMINTERVALFigure 14. HC Head Done Register HCDONEHEAD Table 14. HC Head Done Register HCDONEHEAD Field Descriptions3.15 HC Frame Remaining Register HCFMREMAINING 3.16 HC Frame Number Register HCFMNUMBERFigure 16. HC Frame Remaining Register HCFMREMAINING Figure 17. HC Frame Number Register HCFMNUMBER3.17 HC Periodic Start Register HCPERIODICSTART Figure 18. HC Periodic Start Register HCPERIODICSTARTField Value3.18 HC Low-Speed Threshold Register HCLSTHRESHOLD Figure 19. HC Low-Speed Threshold Register HCLSTHRESHOLDRegisters Field3.19 HC Root Hub A Register HCRHDESCRIPTORA Figure 20. HC Root Hub A Register HCRHDESCRIPTORATable 20. HC Root Hub A Register HCRHDESCRIPTORA Field Descriptions Field3.20 HC Root Hub B Register HCRHDESCRIPTORB Figure 21. HC Root Hub B Register HCRHDESCRIPTORBTable 21. HC Root Hub B Register HCRHDESCRIPTORB Field Descriptions Registers3.21 HC Root Hub Status Register HCRHSTATUS Figure 22. HC Root Hub Status Register HCRHSTATUSTable 22. HC Root Hub Status Register HCRHSTATUS Field Descriptions Field3.22 HC Port 1 Status and Control Register HCRHPORTSTATUS1 Figure 23. HC Port 1 Status and Control Register HCRHPORTSTATUS1Registers FieldPort 1 port power status/set port power. The host controller driver can write a 1 to this bit to set the FieldDescription Submit Documentation Feedback3.23 HC Port 2 Status and Control Register HCRHPORTSTATUS2 Figure 24. HC Port 2 Status and Control Register HCRHPORTSTATUS2Registers FieldSubmit Documentation Feedback FieldDescription Applications IMPORTANT NOTICEProducts