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Texas Instruments TMS320C6747 DSP manual HC Head Done Register HCDONEHEAD

Models: TMS320C6747 DSP

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3.13 HC Head Done Register (HCDONEHEAD)

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Registers

3.13 HC Head Done Register (HCDONEHEAD)

The HC head done register (HCDONEHEAD) defines the physical address of the current head of the done TD queue. HCDONEHEAD is shown in Figure 14 and described in Table 14.

Figure 14. HC Head Done Register (HCDONEHEAD)

31			16
	DH
	R-0
15	4	3	0
DH			Reserved
R-0			R-0

LEGEND: R = Read only; -n= value after reset

Table 14. HC Head Done Register (HCDONEHEAD) Field Descriptions

Bit	Field	Value	Description
31-4	DH	0-FFF FFFFh	Physical address of the last TD that has added to the done queue. This field represents bits 31-4
			of the physical address of the top TD on the done TD queue. TDs are assumed to begin on a
			16-byte aligned address, so bits 3-0 of this pointer are assumed to be 0.
			A value of 0 indicates that there are no TDs on the done queue. This register is automatically
			updated by the USB host controller.
3-0	Reserved	0	Reserved

3.14 HC Frame Interval Register (HCFMINTERVAL)

The HC frame interval register (HCFMINTERVAL) defines the number of 12-MHZ clock pulses in each USB frame. HCFMINTERVAL is shown in Figure 15 and described in Table 15.

			Figure 15. HC Frame Interval Register (HCFMINTERVAL)
31	30			16
FIT				FSMPS
R/W-0				R/W-0
15	14	13		0
Reserved				FRAMEINTERVAL
R-0				R/W-2EDFh
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
		Table 15. HC Frame Interval Register (HCFMINTERVAL) Field Descriptions
Bit	Field		Value	Description
31	FIT		0-1	Frame interval toggle. The host controller driver must toggle this bit any time it changes
				the frame interval field.
30-16	FSMPS		0-7FFFh	Largest data packet. Largest data packet size allowed for full-speed packets, in bit times.
15-14	Reserved		0	Reserved
13-0	FRAMEINTERVAL		0-3FFFh	Frame interval. Number of 12-MHZ clocks in the USB frame. Nominally, this is set to
				11,999 (2EDFh) to give a 1-ms frame. The host controller driver can make minor changes
				to this field to attempt to manually synchronize with another clock source.
SPRUFM8–September 2008				Universal Serial Bus OHCI Host Controller	23
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Texas Instruments TMS320C6747 DSP manual HC Head Done Register HCDONEHEAD, HC Frame Interval Register HCFMINTERVAL

Contents

TMS320C6747 DSP Universal Serial Bus USB OHCI Host Controller Users GuideSubmit Documentation Feedback SPRUFM8-SeptemberContents List of Figures HC HCAA Address Register HCHCCA Field Descriptions List of TablesUSB Host Controller Registers Notational Conventions Read This FirstPreface About This Manual1.1 Purpose of the Peripheral Universal Serial Bus OHCI Host ControllerUsers Guide 1 Introduction2.1.1 Internal System Bus Clocks Needed by the USB1 Module 2.1 USB1 Module Clock and Reset2.1.2 USB1 Module Local Bus Clock and Local Reset 2 Architecture2.2 USB1 Module Open Host Controller Interface Functionality 2.3 USB1 Module Differences From OHCI Specification for USB2.3.1 Power Switching Output Pins Not Supported 2.3.2 Overcurrent Protection Input Pins Not Supported2.4.2 OHCI USB Suspend State 2.4 Implementation of OHCI Specification for USB2.4.1 USB Host Controller Endpoint Descriptor ED List Head Pointers Figure 1. Relationships Between Virtual Address Physical Address 2.6 USB Host Controller Access to System Memory2.5 OHCI Interrupts 2.7 Physical AddressingTable 1. USB Host Controller Registers 3 RegistersFigure 2. OHCI Revision Number Register HCREVISION 3.2 HC Operating Mode Register HCCONTROLFigure 3. HC Operating Mode Register HCCONTROL 3.1 OHCI Revision Number Register HCREVISIONDescription Table 3. HC Operating Mode Register HCCONTROL Field DescriptionsField ValueValue 3.3 HC Command and Status Register HCCOMMANDSTATUSFigure 4. HC Command and Status Register HCCOMMANDSTATUS FieldField 3.4 HC Interrupt and Status Register HCINTERRUPTSTATUSFigure 5. HC Interrupt and Status Register HCINTERRUPTSTATUS RegistersValue Description 3.5 HC Interrupt Enable Register HCINTERRUPTENABLEFigure 6. HC Interrupt Enable Register HCINTERRUPTENABLE FieldField 3.6 HC Interrupt Disable Register HCINTERRUPTDISABLEFigure 7. HC Interrupt Disable Register HCINTERRUPTDISABLE RegistersTable 8. HC HCAA Address Register HCHCCA Field Descriptions 3.7 HC HCAA Address Register HCHCCA3.8 HC Current Periodic Register HCPERIODCURRENTED Figure 8. HC HCAA Address Register HCHCCARegisters 3.9 HC Head Control Register HCCONTROLHEADEDFigure 10. HC Head Control Register HCCONTROLHEADED Table 10. HC Head Control Register HCCONTROLHEADED Field DescriptionsDescription 3.10 HC Current Control Register HCCONTROLCURRENTEDFigure 11. HC Current Control Register HCCONTROLCURRENTED FieldTable 12. HC Head Bulk Register HCBULKHEADED Field Descriptions 3.11 HC Head Bulk Register HCBULKHEADED3.12 HC Current Bulk Register HCBULKCURRENTED Figure 12. HC Head Bulk Register HCBULKHEADEDTable 14. HC Head Done Register HCDONEHEAD Field Descriptions 3.13 HC Head Done Register HCDONEHEAD3.14 HC Frame Interval Register HCFMINTERVAL Figure 14. HC Head Done Register HCDONEHEADFigure 17. HC Frame Number Register HCFMNUMBER 3.15 HC Frame Remaining Register HCFMREMAINING3.16 HC Frame Number Register HCFMNUMBER Figure 16. HC Frame Remaining Register HCFMREMAININGValue 3.17 HC Periodic Start Register HCPERIODICSTARTFigure 18. HC Periodic Start Register HCPERIODICSTART FieldField 3.18 HC Low-Speed Threshold Register HCLSTHRESHOLDFigure 19. HC Low-Speed Threshold Register HCLSTHRESHOLD RegistersField 3.19 HC Root Hub A Register HCRHDESCRIPTORAFigure 20. HC Root Hub A Register HCRHDESCRIPTORA Table 20. HC Root Hub A Register HCRHDESCRIPTORA Field DescriptionsRegisters 3.20 HC Root Hub B Register HCRHDESCRIPTORBFigure 21. HC Root Hub B Register HCRHDESCRIPTORB Table 21. HC Root Hub B Register HCRHDESCRIPTORB Field DescriptionsField 3.21 HC Root Hub Status Register HCRHSTATUSFigure 22. HC Root Hub Status Register HCRHSTATUS Table 22. HC Root Hub Status Register HCRHSTATUS Field DescriptionsField 3.22 HC Port 1 Status and Control Register HCRHPORTSTATUS1Figure 23. HC Port 1 Status and Control Register HCRHPORTSTATUS1 RegistersSubmit Documentation Feedback Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set theField DescriptionField 3.23 HC Port 2 Status and Control Register HCRHPORTSTATUS2Figure 24. HC Port 2 Status and Control Register HCRHPORTSTATUS2 RegistersSubmit Documentation Feedback FieldDescription Applications IMPORTANT NOTICEProducts