Analog Devices ADSP-21020 manual Mrf Mrb = Mrf, = Mrb Mrf = Mrf = Sat Mrf = Sat Mrb

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ADSP-21020

 

 

 

 

 

 

 

 

 

 

 

 

Table V. Multiplier Compute Operations

Rn

 

= Rx * Ry (

 

S

 

 

 

S

 

 

 

F

 

)

Fn

= Fx * Fy

 

 

 

 

 

 

 

MRF

 

 

 

U

 

 

 

U

 

 

 

I

 

 

 

 

MRB

 

 

 

 

 

 

 

 

 

 

 

FR

 

 

 

 

Rn

 

= MRF

+ Rx * Ry (

S

 

S

 

F

 

)

Rn

 

= MRB

 

 

 

 

 

U

 

U

 

I

 

 

MRF

 

= MRF

 

 

 

 

 

 

 

 

 

FR

 

 

 

 

 

 

 

 

 

 

 

 

MRB

 

= MRB

 

 

 

 

 

 

 

 

 

 

 

 

Rn

 

= SAT MRF

 

(SI)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rn

 

= SAT MRB

 

(UI)

 

 

 

 

 

 

 

 

 

MRF

 

= SAT MRF

 

(SF)

 

 

 

 

 

 

 

 

 

MRB

 

= SAT MRB

 

(UF)

 

 

 

 

 

 

 

 

 

MRF

 

= 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MRB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rn

= MRF

– Rx * Ry (

S

Rn

= MRB

 

 

 

U

MRF

= MRF

 

 

 

 

 

 

MRB

= MRB

 

 

 

 

 

 

Rn

= RND MRF

 

(SF)

 

 

 

 

Rn

= RND MRB

 

(UF)

 

 

MRF

= RND MRF

 

 

 

 

 

MRB

= RND MRB

 

 

 

 

 

S F )

UI FR

 

 

MRxF

 

 

 

= Rn

 

 

 

Rn

=

MRxF

 

 

MRxB

 

 

 

 

 

 

 

 

 

 

 

MRxB

Rn, Rx, Ry

 

R15–R0; register file location, fixed-point

 

 

Fn, Fx, Fy

 

F15–F0; register file location, floating-point

 

 

MRxF

 

MR2F, MR1F; MR0F; multiplier result accumulators, foreground

MRxB

 

MR2B, MR1B, MR0B; multiplier result accumulators, background

(

 

x-input

 

 

 

y-input

 

 

 

data format,

 

)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rounding

 

 

 

 

SSigned input

U Unsigned input

I Integer input(s)

F Fractional input(s)

FR

Fractional inputs, Rounded output

(SF)

Default format for 1-input operations

(SSF)

Default format for 2-input operations

Table VI. Shifter and Shifter Immediate Compute Operations

Shifter

Shifter Immediate

Rn = LSHIFT Rx BY Ry

Rn = LSHIFT Rx BY<data8>

Rn = Rn OR LSHIFT Rx BY Ry

Rn = Rn OR LSHIFT Rx BY<data8>

Rn = ASHIFT Rx BY Ry

Rn = ASHIFT Rx BY<data8>

Rn = Rn OR ASHIFT Rx BY Ry

Rn = Rn OR ASHIFT Rx BY<data8>

Rn = ROT Rx BY RY

Rn = ROT Rx BY<data8>

Rn = BCLR Rx BY Ry

Rn = BCLR Rx BY<data8>

Rn = BSET Rx BY Ry

Rn = BSET Rx BY<data8>

Rn = BTGL Rx BY Ry

Rn = BTGL Rx BY<data8>

BTST Rx BY Ry

BTST Rx BY<data8>

Rn = FDEP Rx BY Ry

Rn = FDEP Rx BY <bit6>: <len6>

Rn = Rn OR FDEP Rx BY Ry

Rn = Rn OR FDEP Rx BY <bit6>:<1en6>

Rn = FDEP Rx BY Ry (SE)

Rn = FDEP Rx BY <bit6>:<1en6> (SE)

Rn = Rn OR FDEP Rx BY Ry (SE)

Rn = Rn OR FDEP Rx BY <bit6>:<1en6> (SE)

Rn = FEXT Rx BY Ry

Rn = FEXT Rx BY <bit6>:<1en6>

Rn = FEXT Rx BY Ry (SE)

Rn = FEXT Rx BY <bit6>:<1en6> (SE)

Rn = EXP Rx

 

Rn = EXP Rx (EX)

 

Rn = LEFTZ Rx

 

Rn = LEFTO Rx

 

 

 

Rn, Rx, Ry R15-R0; register file location, fixed-point

<bit6>:<len6> 6-bit immediate bit position and length values (for shifter immediate operations)

–10–

REV. C

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Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Dmts ResetDmpage ClkiinIf condition Compute ComputeIf condition DMIa, Mb = dregItalics Notation MeaningName Description Fixed-Point Floating-Point = MRB MRF = MRF = RND MRF = RND MRB MRF MRB = MRF= MRB MRF = MRF = SAT MRF = SAT MRB Shifter Shifter ImmediateIRQ3 Fixed-PointVector Address Hex Function IRQ2Grade Parameter Min Max Unit Parameter Test Conditions Min Max UnitClkin Period 150 Reset Setup before Clkin High 29 + DT/2Timing Requirement Clkin Width HighPulse Width TCK + Hold after Clkin HighTDTEX Clkin High to Timexp Clkin High to FLAG3-0OUTEnable FLAG3-0INSetup before Clkin High 19 + 5DT/16FLAG3-0OUTDelay from Clkin High Clkin High to FLAG3-0OUTDisableTiming Requirement Memory Interface Disable to LowClkin High to Memory Interface Enable 25 + DT/2 Hold after Clkin HighXTS Delay after Setup before Clkin High 14 + DT/4XTS Delay after Address, Select 28 + 7DT/8 Low 16 + DT/2 Switching CharacteristicXACK Setup before Clkin High + DT/4 XACK Delay from Address + 7DT/8XACK Delay from XRD Low + DT/2 XACK Hold after Clkin High Switching CharacteristicMemory Read Data Setup before XWR High + DT/2 XACK Delay from Address, Select 27 + 7DT/8XACK Delay from XWR Low 15 + DT/2 Data Disable before XWR XRD Low + 3DT/8Memory Write Pulse Width 200 160 132 120 Switching Characteristic TDI, TMS Setup before TCK HighSystem Inputs Setup before TCK High TDO Delay from TCK LowIeee 1149.1 Test Access Port Output disable time tDIS is the difference between Output Enable/DisableCapacitive Loading Pin Type Pins SwitchExample Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W3 0.1 inches Bottom View Ribbon CableADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide