Analog Devices ADSP-21020 manual Inches Millimeters Symbol MIN MAX

Page 31

ADSP-21020

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

223-Pin Ceramic Pin Grid Array

TOP VIEW

A B C D E F G H J K L M N P R S T U

φ b	e	φ b
		1

		INCHES		MILLIMETERS

SYMBOL	MIN		MAX	MIN	MAX

A	0.084		0.102	2.11	2.59

A1	0.40		0.60	1.02	1.52

φb	0.018 TYP			0.46 TYP

φb1	0.050 TYP			1.27 TYP

D	1.844		1.876	46.84	47.64

e1	1.700 TYP			43.18 TYP

e	0.100 TYP			2.54 TYP

L3	0.172		0.188	4.37	4.77

h	0.020 TYP			0.500 TYP

j1	1.125		1.147	28.56	29.14
j2	1.065		1.186	27.05	27.61

NOTE

When socketing the CPGA package, use of a low insertion force socket is recommended.

REV. C

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Image 31

Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Clkiin ResetDmpage DmtsDMIa, Mb = dreg ComputeIf condition If condition ComputeItalics Notation MeaningName Description Fixed-Point Floating-Point Shifter Shifter Immediate MRF MRB = MRF= MRB MRF = MRF = SAT MRF = SAT MRB = MRB MRF = MRF = RND MRF = RND MRBIRQ2 Fixed-PointVector Address Hex Function IRQ3Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitClkin Width High Reset Setup before Clkin High 29 + DT/2Timing Requirement Clkin Period 150Pulse Width TCK + Hold after Clkin HighTDTEX Clkin High to Timexp Clkin High to FLAG3-0OUTDisable FLAG3-0INSetup before Clkin High 19 + 5DT/16FLAG3-0OUTDelay from Clkin High Clkin High to FLAG3-0OUTEnableHold after Clkin High Memory Interface Disable to LowClkin High to Memory Interface Enable 25 + DT/2 Timing RequirementLow 16 + DT/2 Switching Characteristic Setup before Clkin High 14 + DT/4XTS Delay after Address, Select 28 + 7DT/8 XTS Delay afterXACK Hold after Clkin High Switching Characteristic XACK Delay from Address + 7DT/8XACK Delay from XRD Low + DT/2 XACK Setup before Clkin High + DT/4Memory Read Data Disable before XWR XRD Low + 3DT/8 XACK Delay from Address, Select 27 + 7DT/8XACK Delay from XWR Low 15 + DT/2 Data Setup before XWR High + DT/2Memory Write TDO Delay from TCK Low TDI, TMS Setup before TCK HighSystem Inputs Setup before TCK High Pulse Width 200 160 132 120 Switching CharacteristicIeee 1149.1 Test Access Port Output Enable/Disable Output disable time tDIS is the difference betweenCapacitive Loading Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W Type Pins SwitchExample PinBottom View Ribbon Cable 3 0.1 inchesADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide

ADSP-21020

OUTLINE DIMENSIONS

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

REV. C