Analog Devices ADSP-21020 manual Timing Requirement1, FLAG3-0INSetup before Clkin High 19 + 5DT/16

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ADSP-21020

Flags

 

 

 

 

 

 

 

 

 

 

K/B/T Grade

K/B/T Grade

B/T Grade

K Grade

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20 MHz

25 MHz

30 MHz

33.3 MHz

Frequency Dependency*

 

Parameter

Min Max

Min Max

Min Max

Min Max

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timing Requirement:1

 

 

 

 

 

 

 

tSFI

FLAG3-0INSetup before CLKIN High

19

16

14

13

19 + 5DT/16

ns

tHFI

FLAG3-0INHold after CLKIN High

0

0

0

0

 

 

ns

tDWRFI FLAG3-0INDelay from

xRD

,

xWR

Low

12

8

5

3

 

12 + 7DT/16

ns

tHFIWR FLAG3-0INHold after

xRD

,

xWR

 

0

0

0

0

 

 

ns

 

Deasserted

 

 

 

 

 

 

 

Switching Characteristic:

 

 

 

 

 

 

 

tDFO

FLAG3-0OUTDelay from CLKIN High

24

24

24

24

 

 

ns

tHFO

FLAG3-0OUTHold after CLKIN High

5

5

5

5

 

 

ns

tDFOE

CLKIN High to FLAG3-0OUTEnable

1

1

1

1

 

 

ns

tDFOD

CLKIN High to FLAG3-0OUTDisable

24

24

24

24

 

 

ns

NOTES

*DT = tCK – 50 ns

1Flag inputs meeting these setup and hold times will affect conditional operations in the next instruction cycle. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for additional flag servicing information.

x = PM or DM.

CLKIN

 

tDFO

tDFO

tDFOD

tDFOE

tHFO

FLAG3-0OUT

CLKIN

tSFI

FLAG OUTPUT

tHFI

FLAG3-0 IN

tDWRFI

xRD, xWR

tHFIWR

FLAG INPUT

Figure 7. Flags

REV. C

–15–

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Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Clkiin ResetDmpage DmtsDMIa, Mb = dreg ComputeIf condition If condition ComputeNotation Meaning ItalicsName Description Fixed-Point Floating-Point Shifter Shifter Immediate MRF MRB = MRF= MRB MRF = MRF = SAT MRF = SAT MRB = MRB MRF = MRF = RND MRF = RND MRBIRQ2 Fixed-PointVector Address Hex Function IRQ3Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitClkin Width High Reset Setup before Clkin High 29 + DT/2Timing Requirement Clkin Period 150Hold after Clkin High Pulse Width TCK +TDTEX Clkin High to Timexp Clkin High to FLAG3-0OUTDisable FLAG3-0INSetup before Clkin High 19 + 5DT/16FLAG3-0OUTDelay from Clkin High Clkin High to FLAG3-0OUTEnableHold after Clkin High Memory Interface Disable to LowClkin High to Memory Interface Enable 25 + DT/2 Timing RequirementLow 16 + DT/2 Switching Characteristic Setup before Clkin High 14 + DT/4XTS Delay after Address, Select 28 + 7DT/8 XTS Delay afterXACK Hold after Clkin High Switching Characteristic XACK Delay from Address + 7DT/8XACK Delay from XRD Low + DT/2 XACK Setup before Clkin High + DT/4Memory Read Data Disable before XWR XRD Low + 3DT/8 XACK Delay from Address, Select 27 + 7DT/8XACK Delay from XWR Low 15 + DT/2 Data Setup before XWR High + DT/2Memory Write TDO Delay from TCK Low TDI, TMS Setup before TCK HighSystem Inputs Setup before TCK High Pulse Width 200 160 132 120 Switching CharacteristicIeee 1149.1 Test Access Port Output Enable/Disable Output disable time tDIS is the difference betweenCapacitive Loading Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W Type Pins SwitchExample PinBottom View Ribbon Cable 3 0.1 inchesADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide