Analog Devices ADSP-21020 manual Capacitive Loading

Page 25

Capacitive Loading

Output delays are based on standard capacitive loads: 100 pF on address, select, page and strobe pins, and 50 pF on all others (see Figure 14). For different loads, these timing parameters should be derated. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for further information on derating of timing specifications.

Figures 16 and 17 show how the output rise time varies with capacitance. Figures 18 and 19 show how output delays vary with capacitance. Note that the graphs may not be linear outside the ranges shown.

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

 

 

9.18

 

 

 

 

 

 

 

 

 

 

 

 

2.0V)

8

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(0.8V

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

– ns

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.95

 

TIME

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RISE

3

 

 

 

 

 

 

 

 

 

 

2

 

1.46

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1.31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

25

50

75

100

125

150

175

200

 

 

 

 

 

 

 

LOAD CAPACITANCE – pF

 

 

 

NOTES:

(1)OUTPUT PINS BG, TIMEXP

(2)OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0

Figure 16. Typical Output Rise Time vs. Load Capacitance (at Maximum Case Temperature)

2.0V)

4

 

 

 

 

 

 

 

3.59

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

(0.8V

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

– ns

 

 

 

 

 

 

 

 

3.00

 

2

 

 

 

 

 

2

 

 

 

TIME

1.33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RISE

1

0.85

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

π

 

 

 

 

 

 

 

 

 

 

25

50

75

100

125

150

175

200

LOAD CAPACITANCE – pF

NOTES:

(1)OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO

(2)OUTPUT PINS PMRD, PMWR, DMRD, DMWR

Figure 17. Typical Output Rise Time vs. Load Capacitance (at Maximum Case Temperature)

ADSP-21020

 

12

 

 

 

 

 

 

 

 

11.19

 

 

 

 

 

 

 

 

 

 

 

 

– ns

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HOLDOR

8

 

 

 

 

 

 

 

 

 

 

DELAY

 

 

 

 

 

 

 

1

 

 

 

6

 

 

 

 

 

 

 

 

5.34

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

NOMINAL

 

– 0.89

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–2

 

–1.86

 

 

 

 

 

 

 

 

 

25

50

75

100

125

150

175

200

 

 

LOAD CAPACITANCE – pF

NOTES:

(1)OUTPUT PINS BG, TIMEXP

(2)OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0

Figure 18. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature)

– ns

3

 

 

 

 

 

 

 

2.99

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

HOLD

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OR

1

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

DELAY

NOMINAL

 

 

 

 

 

 

 

 

 

OUTPUT

–1

– 1.70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–2

 

 

 

 

 

 

 

 

 

 

 

– 2.24

 

 

 

 

 

 

 

 

 

–3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

50

75

100

125

150

175

200

LOAD CAPACITANCE – pF

NOTES:

(1)OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO

(2)OUTPUT PINS PMRD, PMWR, DMRD, DMWR

Figure 19. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature)

REV. C

–25–

Image 25
Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Dmpage ResetDmts ClkiinIf condition ComputeIf condition Compute DMIa, Mb = dregItalics Notation MeaningName Description Fixed-Point Floating-Point = MRB MRF = MRF = SAT MRF = SAT MRB MRF MRB = MRF= MRB MRF = MRF = RND MRF = RND MRB Shifter Shifter ImmediateVector Address Hex Function Fixed-PointIRQ3 IRQ2Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitTiming Requirement Reset Setup before Clkin High 29 + DT/2Clkin Period 150 Clkin Width HighPulse Width TCK + Hold after Clkin HighTDTEX Clkin High to Timexp FLAG3-0OUTDelay from Clkin High FLAG3-0INSetup before Clkin High 19 + 5DT/16Clkin High to FLAG3-0OUTEnable Clkin High to FLAG3-0OUTDisableClkin High to Memory Interface Enable 25 + DT/2 Memory Interface Disable to LowTiming Requirement Hold after Clkin HighXTS Delay after Address, Select 28 + 7DT/8 Setup before Clkin High 14 + DT/4XTS Delay after Low 16 + DT/2 Switching CharacteristicXACK Delay from XRD Low + DT/2 XACK Delay from Address + 7DT/8XACK Setup before Clkin High + DT/4 XACK Hold after Clkin High Switching CharacteristicMemory Read XACK Delay from XWR Low 15 + DT/2 XACK Delay from Address, Select 27 + 7DT/8Data Setup before XWR High + DT/2 Data Disable before XWR XRD Low + 3DT/8Memory Write System Inputs Setup before TCK High TDI, TMS Setup before TCK HighPulse Width 200 160 132 120 Switching Characteristic TDO Delay from TCK LowIeee 1149.1 Test Access Port Output Enable/Disable Output disable time tDIS is the difference betweenCapacitive Loading Example Type Pins SwitchPin Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 WBottom View Ribbon Cable 3 0.1 inchesADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide