Analog Devices ADSP-21020 manual Output disable time tDIS is the difference between

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ADSP-21020

TEST CONDITIONS

Output Disable Time

Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ΔV is dependent on the capacitive load, CL, and the load current, IL. It can be approximated by the following equation:

tDECAY = CL ΔV

IL

The output disable time (tDIS) is the difference between

tMEASURED and tDECAY as shown in Figure 13. The time tMEASURED) is the interval from when the reference signal switches to when the output voltage decays ΔV from the

measured output high or output low voltage. tDECAY is calculated with ΔV equal to 0.5 V, and test loads CL and IL.

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate tDECAY using the above equation. Choose ΔV to be the difference between the ADSP-21020’s output voltage and

the input threshold for the device requiring the hold time. A typical ΔV will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per

data line). The hold time will be tDECAY plus the minimum disable time (i.e. tHDWD for the write cycle).

IOL

TO

OUTPUT +1.5V PIN

50pF*

IOH

*AC TIMING SPECIFICATIONS ARE CALCULATED FOR 100pF DERATING ON THE FOLLOWING PINS: PMA23–0,PMS1–0,PMRD,

PMWR, PMPAGE, DMA31–0, DMS3–0, DMRD, DMWR, DMPAGE

Figure 14. Equivalent Device Loading For AC Measurements (Includes All Fixtures)

INPUT OR

1.5V

1.5V

 

OUTPUT

Figure 15. Voltage Reference Levels For AC Measurements (Except Output Enable/Disable)

REFERENCE

 

 

SIGNAL

 

 

 

t MEASURED

 

t DIS

 

tENA

VOH (MEASURED)

 

VOH (MEASURED)

 

VOH (MEASURED) ΔV

2.0V

 

 

OUTPUT

 

 

 

VOL (MEASURED) +ΔV

1.0V

VOL (MEASURED)

 

VOL (MEASURED)

tDECAY

OUTPUT STOPS DRIVING

HIGH-IMPEDANCE STATE. TEST CONDITIONS

OUTPUT STARTS DRIVING

CAUSE THIS VOLTAGE LEVEL TO BE

 

 

 

APPROXIMATELY 1.5 V.

 

Figure 13. Output Enable/Disable

–24–

REV. C

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Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Reset DmpageDmts ClkiinCompute If conditionIf condition Compute DMIa, Mb = dregNotation Meaning ItalicsName Description Fixed-Point Floating-Point MRF MRB = MRF = MRB MRF = MRF = SAT MRF = SAT MRB= MRB MRF = MRF = RND MRF = RND MRB Shifter Shifter ImmediateFixed-Point Vector Address Hex FunctionIRQ3 IRQ2Grade Parameter Min Max Unit Parameter Test Conditions Min Max UnitReset Setup before Clkin High 29 + DT/2 Timing RequirementClkin Period 150 Clkin Width HighHold after Clkin High Pulse Width TCK +TDTEX Clkin High to Timexp FLAG3-0INSetup before Clkin High 19 + 5DT/16 FLAG3-0OUTDelay from Clkin HighClkin High to FLAG3-0OUTEnable Clkin High to FLAG3-0OUTDisableMemory Interface Disable to Low Clkin High to Memory Interface Enable 25 + DT/2Timing Requirement Hold after Clkin HighSetup before Clkin High 14 + DT/4 XTS Delay after Address, Select 28 + 7DT/8XTS Delay after Low 16 + DT/2 Switching CharacteristicXACK Delay from Address + 7DT/8 XACK Delay from XRD Low + DT/2XACK Setup before Clkin High + DT/4 XACK Hold after Clkin High Switching CharacteristicMemory Read XACK Delay from Address, Select 27 + 7DT/8 XACK Delay from XWR Low 15 + DT/2Data Setup before XWR High + DT/2 Data Disable before XWR XRD Low + 3DT/8Memory Write TDI, TMS Setup before TCK High System Inputs Setup before TCK HighPulse Width 200 160 132 120 Switching Characteristic TDO Delay from TCK LowIeee 1149.1 Test Access Port Output disable time tDIS is the difference between Output Enable/DisableCapacitive Loading Type Pins Switch ExamplePin Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W3 0.1 inches Bottom View Ribbon CableADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide