Analog Devices ADSP-21020 manual Timing Requirement, Hold after Clkin High, Clkin High to Low

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ADSP-21020

Bus Request/Bus Grant

K/B/T Grade

B/T Grade

K Grade

20 MHz

25 MHz

30 MHz

33.3 MHz

Frequency Dependency*

Parameter

Min Max

Min

Max

Unit

Timing Requirement:

tHBR

Hold after CLKIN High

tSBR

Setup before CLKIN High

18 + 5DT/16

Switching Characteristic:

tDMDBGL

Memory Interface Disable to

Low

–2

tDME

CLKIN High to Memory Interface

Enable

25 + DT/2

tDBGL

CLKIN High to

Low

tDBGH

CLKIN High to

High

NOTES

*DT = tCK – 50 ns.

Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE. Buses are not granted until completion of current memory access.

See the Memory Interface chapter of the ADSP-21020 User’s Manual for BG, BR cycle relationships.

CLKIN

t HBR

tSBR

t HBR

tSBR

tDME

MEMORY

INTERFACE

tDMDBGL

tDBGL

tDBGH

Figure 8. Bus Request/Bus Grant

–16–

REV. C

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Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Reset DmpageDmts ClkiinCompute If conditionIf condition Compute DMIa, Mb = dregItalics Notation MeaningName Description Fixed-Point Floating-Point MRF MRB = MRF = MRB MRF = MRF = SAT MRF = SAT MRB= MRB MRF = MRF = RND MRF = RND MRB Shifter Shifter ImmediateFixed-Point Vector Address Hex FunctionIRQ3 IRQ2Grade Parameter Min Max Unit Parameter Test Conditions Min Max UnitReset Setup before Clkin High 29 + DT/2 Timing RequirementClkin Period 150 Clkin Width HighPulse Width TCK + Hold after Clkin HighTDTEX Clkin High to Timexp FLAG3-0INSetup before Clkin High 19 + 5DT/16 FLAG3-0OUTDelay from Clkin HighClkin High to FLAG3-0OUTEnable Clkin High to FLAG3-0OUTDisableMemory Interface Disable to Low Clkin High to Memory Interface Enable 25 + DT/2Timing Requirement Hold after Clkin HighSetup before Clkin High 14 + DT/4 XTS Delay after Address, Select 28 + 7DT/8XTS Delay after Low 16 + DT/2 Switching CharacteristicXACK Delay from Address + 7DT/8 XACK Delay from XRD Low + DT/2XACK Setup before Clkin High + DT/4 XACK Hold after Clkin High Switching CharacteristicMemory Read XACK Delay from Address, Select 27 + 7DT/8 XACK Delay from XWR Low 15 + DT/2Data Setup before XWR High + DT/2 Data Disable before XWR XRD Low + 3DT/8Memory Write TDI, TMS Setup before TCK High System Inputs Setup before TCK HighPulse Width 200 160 132 120 Switching Characteristic TDO Delay from TCK LowIeee 1149.1 Test Access Port Output disable time tDIS is the difference between Output Enable/DisableCapacitive Loading Type Pins Switch ExamplePin Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W3 0.1 inches Bottom View Ribbon CableADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide