Analog Devices ADSP-21020 manual Address, Select to Data Valid + DT, XRD Low to Data Valid + 5DT/8

Page 18

ADSP-21020

Memory Read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K/B/T Grade

K/B/T Grade

B/T Grade

K Grade

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20 MHz

25 MHz

30 MHz

33.3 MHz

Frequency Dependence*

 

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timing Requirement:

 

 

 

 

 

 

 

 

 

 

 

 

 

tDAD

Address, Select to Data Valid

 

37

 

27

 

20

 

17

 

 

37

+ DT

ns

tDRLD

xRD

Low to Data Valid

 

24

 

18

 

13

 

11

 

 

24

+ 5DT/8

ns

tHDA

Data Hold from Address, Select

0

 

0

 

0

 

0

 

 

 

 

 

ns

tHDRH

Data Hold from

xRD

 

High

–1

 

–1

 

–1

 

–1

 

 

 

 

 

ns

tDAAK

xACK Delay from Address

 

27

 

18

 

12

 

9

 

 

27

+ 7DT/8

ns

tDRAK

xACK Delay from

xRD

Low

 

15

 

10

 

6

 

5

 

 

15

+ DT/2

ns

tSAK

xACK Setup before CLKIN High

14

 

12

 

10

 

9

 

14

+ DT/4

 

 

ns

tHAK

xACK Hold after CLKIN High

0

 

0

 

0

 

0

 

 

 

 

 

ns

Switching Characteristic:

 

 

 

 

 

 

 

 

 

 

 

 

 

tDARL

Address, Select to

 

 

 

Low

8

 

4

 

2

 

0

 

8 + 3DT/8

 

 

ns

xRD

 

 

 

 

 

 

tDAP

xPAGE Delay from Address, Select

 

1

 

1

 

1

 

1

 

 

 

 

ns

tDCKRL

CLKIN High to

xRD

Low

16

26

13

24

12

22

11

21

16

+ DT/4

26 + DT/4

ns

tRW

xRD

Pulse Width

26

 

20

 

15

 

13

 

26

+ 5DT/8

 

 

ns

tRWR

xRD

High to

xRD

,

xWD

Low

17

 

13

 

11

 

9

 

17

+ 3DT/8

 

 

ns

NOTES

*DT = tCK – 50 ns

x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select = PMS1-0, DMS3-0.

–18–

REV. C

Image 18
Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Dmts ResetDmpage ClkiinIf condition Compute ComputeIf condition DMIa, Mb = dregNotation Meaning ItalicsName Description Fixed-Point Floating-Point = MRB MRF = MRF = RND MRF = RND MRB MRF MRB = MRF= MRB MRF = MRF = SAT MRF = SAT MRB Shifter Shifter ImmediateIRQ3 Fixed-PointVector Address Hex Function IRQ2Grade Parameter Min Max Unit Parameter Test Conditions Min Max UnitClkin Period 150 Reset Setup before Clkin High 29 + DT/2Timing Requirement Clkin Width HighHold after Clkin High Pulse Width TCK +TDTEX Clkin High to Timexp Clkin High to FLAG3-0OUTEnable FLAG3-0INSetup before Clkin High 19 + 5DT/16FLAG3-0OUTDelay from Clkin High Clkin High to FLAG3-0OUTDisableTiming Requirement Memory Interface Disable to LowClkin High to Memory Interface Enable 25 + DT/2 Hold after Clkin HighXTS Delay after Setup before Clkin High 14 + DT/4XTS Delay after Address, Select 28 + 7DT/8 Low 16 + DT/2 Switching CharacteristicXACK Setup before Clkin High + DT/4 XACK Delay from Address + 7DT/8XACK Delay from XRD Low + DT/2 XACK Hold after Clkin High Switching CharacteristicMemory Read Data Setup before XWR High + DT/2 XACK Delay from Address, Select 27 + 7DT/8XACK Delay from XWR Low 15 + DT/2 Data Disable before XWR XRD Low + 3DT/8Memory Write Pulse Width 200 160 132 120 Switching Characteristic TDI, TMS Setup before TCK HighSystem Inputs Setup before TCK High TDO Delay from TCK LowIeee 1149.1 Test Access Port Output disable time tDIS is the difference between Output Enable/DisableCapacitive Loading Pin Type Pins SwitchExample Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W3 0.1 inches Bottom View Ribbon CableADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide