Analog Devices ADSP-21020 manual Notation Meaning, Italics, Name Description

Page 8

ADSP-21020

IMMEDIATE MOVE INSTRUCTIONS

14a. DM(<addr32>) = ureg ; PM(<addr24>)

14b. ureg =

DM(<addr32>)

;

 

PM(<addr24>)

 

15a. DM(<data32>, Ia) = ureg; PM(< data24>, Ic)

15b. ureg =

DM(<data32>, Ia)

;

 

PM(<data24>, Ic)

 

16.DM(Ia, Mb) = <data32>; PM(Ic, Md)

17.ureg = <data32>;

MISCELLANEOUS INSTRUCTIONS

 

 

18.

BIT

 

SET

 

 

sreg <data32>;

 

 

 

 

 

 

 

 

 

 

 

 

 

CLR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TGL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XOR

 

 

 

 

 

 

 

 

 

19a. MODIFY

 

 

(Ia, <data32>)

 

;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Ic, <data32>)

 

 

 

 

 

 

19b. BITREV

 

(Ia, <data32>)

;

 

 

 

20.

 

PUSH

 

 

 

LOOP

,

 

 

 

PUSH

 

STS ;

 

 

 

 

 

 

 

 

 

POP

 

 

 

 

 

 

 

 

 

 

POP

 

 

21.NOP ;

22.IDLE ;

Table I. Syntax Notation Conventions

Notation

Meaning

UPPERCASE

Explicit syntax—assembler keyword (nota-

 

tion only; assembler is not case-sensitive

 

and lowercase is the preferred programming

 

convention)

;

Instruction terminator

,

Separates parallel operations in an

 

instruction

italics

Optional part of instruction

between lines

List of options (choose one)

<datan>

n-bit immediate data value

<addrn>

n-bit immediate address value

<reladdrn>

n-bit immediate PC-relative address value

compute

ALU, multiplier, shifter or multifunction

 

operation (from Tables IV-VII)

shiftimm

Shifter immediate operation

 

(from Table VI)

condition

Status condition (from Table II)

termination

Termination condition (from Table II)

ureg

Universal register (from Table III)

sreg

System register (from Table III)

dreg

R15-R0, F15-F0; register file location

Ia

I7-I0; DAG1 index register

Mb

M7-M0; DAG1 modify register

Ic

I15-I8; DAG2 index register

Md

M15-M8; DAG2 modify register

 

 

Table II. Condition and Termination Codes

 

 

Name

Description

 

 

eq

ALU equal to zero

ne

ALU not equal to zero

ge

ALU greater than or equal to zero

lt

ALU less than zero

le

ALU less than or equal to zero

gt

ALU greater than zero

ac

ALU carry

not ac

Not ALU carry

av

ALU overflow

not av

Not ALU overflow

mv

Multiplier overflow

not mv

Not multiplier overflow

ms

Multiplier sign

not ms

Not multiplier sign

sv

Shifter overflow

not sv

Not shifter overflow

sz

Shifter zero

not sz

Not shifter zero

flag0_in

Flag 0

not flag0_in

Not Flag 0

flag1_in

Flag 1

not flag1_in

Not Flag l

flag2_in

Flag 2

not flag2_in

Not Flag 2

flag3_in

Flag 3

not flag3_in

Not Flag 3

tf

Bit test flag

not tf

Not bit test flag

lce

Loop counter expired (DO UNTIL)

not lce

Loop counter not expired (IF)

forever

Always False (DO UNTIL)

true

Always True (IF)

 

 

In a conditional instruction, the execution of the entire instruction is based on the specified condition.

–8–

REV. C

Image 8
Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Reset DmpageDmts ClkiinCompute If conditionIf condition Compute DMIa, Mb = dregName Description Notation MeaningItalics Fixed-Point Floating-Point MRF MRB = MRF = MRB MRF = MRF = SAT MRF = SAT MRB= MRB MRF = MRF = RND MRF = RND MRB Shifter Shifter ImmediateFixed-Point Vector Address Hex FunctionIRQ3 IRQ2Grade Parameter Min Max Unit Parameter Test Conditions Min Max UnitReset Setup before Clkin High 29 + DT/2 Timing RequirementClkin Period 150 Clkin Width HighTDTEX Clkin High to Timexp Hold after Clkin HighPulse Width TCK + FLAG3-0INSetup before Clkin High 19 + 5DT/16 FLAG3-0OUTDelay from Clkin HighClkin High to FLAG3-0OUTEnable Clkin High to FLAG3-0OUTDisableMemory Interface Disable to Low Clkin High to Memory Interface Enable 25 + DT/2Timing Requirement Hold after Clkin HighSetup before Clkin High 14 + DT/4 XTS Delay after Address, Select 28 + 7DT/8XTS Delay after Low 16 + DT/2 Switching CharacteristicXACK Delay from Address + 7DT/8 XACK Delay from XRD Low + DT/2XACK Setup before Clkin High + DT/4 XACK Hold after Clkin High Switching CharacteristicMemory Read XACK Delay from Address, Select 27 + 7DT/8 XACK Delay from XWR Low 15 + DT/2Data Setup before XWR High + DT/2 Data Disable before XWR XRD Low + 3DT/8Memory Write TDI, TMS Setup before TCK High System Inputs Setup before TCK HighPulse Width 200 160 132 120 Switching Characteristic TDO Delay from TCK LowIeee 1149.1 Test Access Port Output disable time tDIS is the difference between Output Enable/DisableCapacitive Loading Type Pins Switch ExamplePin Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W3 0.1 inches Bottom View Ribbon CableADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide