Analog Devices ADSP-21020 Hold after Clkin High, Pulse Width TCK +, TDTEX Clkin High to Timexp

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ADSP-21020

Interrupts

 

 

 

 

K/B/T Grade

K/B/T Grade

B/T Grade

K Grade

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20 MHz

25 MHz

30 MHz

33.3 MHz

Frequency Dependency*

 

Parameter

 

Min Max

Min Max

Min Max

Min Max

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

Timing Requirement:

 

 

 

 

 

 

 

tSIR IRQ3-0

Setup before CLKIN High

38

31

25

23

38 + 3DT/4

 

ns

tHIR

IRQ

3-0

Hold after CLKIN High

0

0

0

0

 

ns

 

tIPW

IRQ

3-0

Pulse Width

55

45

38

35

tCK + 5

 

ns

NOTE

*DT = tCK – 50 ns

Meeting setup and hold guarantees interrupts will be latched in that cycle. Meeting the pulse width is not necessary if the setup and hold is met. Likewise, meeting the setup and hold is not necessary if the pulse width is met. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for interrupt servicing informa- tion.

CLKIN

 

 

 

 

t

SIR

tHIR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRQ3-0

 

 

 

 

 

 

 

 

 

 

 

 

tIPW

 

 

 

 

 

 

 

Figure 5. Interrupts

 

 

 

 

Timer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K/B/T Grade

K/B/T Grade

 

B/T Grade

K Grade

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20 MHz

25 MHz

 

30 MHz

33.3 MHz

Frequency Dependency*

 

Parameter

 

Min Max

Min Max

 

Min Max

Min Max

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

Switching Characteristic:

 

 

 

 

 

 

 

 

 

tDTEX CLKIN High to TIMEXP

 

24

24

 

24

24

 

 

ns

NOTE

 

 

 

 

 

 

 

 

 

*DT = tCK – 50 ns

 

 

 

 

 

 

 

 

 

 

CLKIN

 

 

 

 

 

 

 

 

 

t DTEX

 

 

 

tDTEX

 

 

 

TIMEXP

Figure 6. TIMEXP

–14–

REV. C

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Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Dmts ResetDmpage ClkiinIf condition Compute ComputeIf condition DMIa, Mb = dregName Description Notation MeaningItalics Fixed-Point Floating-Point = MRB MRF = MRF = RND MRF = RND MRB MRF MRB = MRF= MRB MRF = MRF = SAT MRF = SAT MRB Shifter Shifter Immediate IRQ3 Fixed-Point Vector Address Hex Function IRQ2Grade Parameter Min Max Unit Parameter Test Conditions Min Max UnitClkin Period 150 Reset Setup before Clkin High 29 + DT/2Timing Requirement Clkin Width HighTDTEX Clkin High to Timexp Hold after Clkin HighPulse Width TCK + Clkin High to FLAG3-0OUTEnable FLAG3-0INSetup before Clkin High 19 + 5DT/16FLAG3-0OUTDelay from Clkin High Clkin High to FLAG3-0OUTDisableTiming Requirement Memory Interface Disable to LowClkin High to Memory Interface Enable 25 + DT/2 Hold after Clkin HighXTS Delay after Setup before Clkin High 14 + DT/4XTS Delay after Address, Select 28 + 7DT/8 Low 16 + DT/2 Switching CharacteristicXACK Setup before Clkin High + DT/4 XACK Delay from Address + 7DT/8XACK Delay from XRD Low + DT/2 XACK Hold after Clkin High Switching CharacteristicMemory Read Data Setup before XWR High + DT/2 XACK Delay from Address, Select 27 + 7DT/8XACK Delay from XWR Low 15 + DT/2 Data Disable before XWR XRD Low + 3DT/8Memory Write Pulse Width 200 160 132 120 Switching Characteristic TDI, TMS Setup before TCK HighSystem Inputs Setup before TCK High TDO Delay from TCK LowIeee 1149.1 Test Access Port Output disable time tDIS is the difference between Output Enable/DisableCapacitive Loading Pin Type Pins SwitchExample Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W3 0.1 inches Bottom View Ribbon CableADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide