Analog Devices ADSP-21020 manual Fixed-Point, Vector Address Hex Function, IRQ3, IRQ2, IRQ0

Page 11

ADSP-21020

Table Vll. Multifunction Compute Operations

Fixed-Point

Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=R11-8R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8R15-12 MRF=MRF + R3-0 * R7-4 (SSF), Ra=(R11-8 + R15-12)/2 Rm=MRF + R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Rm=MRF + R3-0 * R7-4 (SSFR), Ra=R11-8R15-12 Rm=MRF + R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 MRF=MRF – R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12 MRF=MRF – R3-0 * R7-4 (SSF), Ra=R11-8R15-12 MRF=MRF – R3-0 * R7-4 (SSF), Ra=(R11-8 + R15-12)/2 Rm=MRF – R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Rm=MRF – R3-0 * R7-4 (SSFR), Ra=R11-8R15-12 Rm=MRF – R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12,

Rs=R11-8R15-12

Floating-Point

Fm=F3-0 * F7-4, Fa=F11-8 + F15-12 Fm=F3-0 * F7-4, Fa=F11-8F15-12 Fm=F3-0 * F7-4, Fa=FLOAT R11-8 by R15-12 Fm=F3-0 * F7-4, Fa=FIX R11-8 by R15-12 Fm=F3-0 * F7-4, Fa=(F11-8 + F15-12)/2 Fm=F3-0 * F7-4, Fa=ABS F11-8

Fm=F3-0 * F7-4, Fa=MAX (F11-8, F15-12) Fm=F3-0 * F7-4, Fa=MIN (F11-8, F15-12) Fm=F3-0 * F7-4, Fa=F11-8 + F15-12,

Fs=F11-8F15-12

Ra, Rm

Any register file location (fixed-point)

R3-0

R3, R2, R1, R0

R7-4

R7, R6, R5, R4

R11-8

R11, R10, R9, R8

R15-12

R15, R14, R13, R12

Fa, Fm

Any register file location (floating-point)

F3-0

F3, F2, F1, F0

F7-4

F7, F6, F5, F4

F11-8

F11, F10, F9, F8

F15-12

F15, F14, F13, F12

(SSF)

X-input signed, Y-input signed, fractional inputs

(SSFR)

X-input signed, Y-input signed, fractional inputs, rounded output

Table VIII. Interrupt Vector Addresses and Priorities

 

Vector

 

 

 

 

Address

 

 

 

No.

(Hex)

Function

 

 

 

 

 

0

0x00

 

Reserved

1*

0x08

 

Reset

2

0xl0

 

Reserved

3

0xl8

Status stack or loop stack overflow or

 

 

PC stack full

4

0x20

Timer=0 (high priority option)

5

0x28

 

IRQ3

asserted

6

0x30

 

IRQ2

asserted

7

0x38

 

IRQ1 asserted

8

0x40

 

IRQ0

asserted

9

0x48

 

Reserved

10

0x50

 

Reserved

11

0x58

DAG 1 circular buffer 7 overflow

12

0x60

DAG 2 circular buffer 15 overflow

13

0x68

 

Reserved

14

0x70

Timer=0 (low priority option)

15

0x78

Fixed-point overflow

16

0x80

Floating-point overflow

17

0x88

Floating-point underflow

18

0x90

Floating-point invalid operation

19–23

0x98-0xB8

Reserved

24–31

0xC0–OxF8

User software interrupts

 

 

 

 

 

*Nonmaskable

REV. C

–11–

Image 11
Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Clkiin ResetDmpage DmtsDMIa, Mb = dreg ComputeIf condition If condition Compute Name Description Notation Meaning Italics Fixed-Point Floating-Point Shifter Shifter Immediate MRF MRB = MRF= MRB MRF = MRF = SAT MRF = SAT MRB = MRB MRF = MRF = RND MRF = RND MRBIRQ2 Fixed-PointVector Address Hex Function IRQ3Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitClkin Width High Reset Setup before Clkin High 29 + DT/2Timing Requirement Clkin Period 150TDTEX Clkin High to Timexp Hold after Clkin HighPulse Width TCK + Clkin High to FLAG3-0OUTDisable FLAG3-0INSetup before Clkin High 19 + 5DT/16FLAG3-0OUTDelay from Clkin High Clkin High to FLAG3-0OUTEnableHold after Clkin High Memory Interface Disable to LowClkin High to Memory Interface Enable 25 + DT/2 Timing RequirementLow 16 + DT/2 Switching Characteristic Setup before Clkin High 14 + DT/4XTS Delay after Address, Select 28 + 7DT/8 XTS Delay afterXACK Hold after Clkin High Switching Characteristic XACK Delay from Address + 7DT/8XACK Delay from XRD Low + DT/2 XACK Setup before Clkin High + DT/4Memory Read Data Disable before XWR XRD Low + 3DT/8 XACK Delay from Address, Select 27 + 7DT/8XACK Delay from XWR Low 15 + DT/2 Data Setup before XWR High + DT/2Memory Write TDO Delay from TCK Low TDI, TMS Setup before TCK HighSystem Inputs Setup before TCK High Pulse Width 200 160 132 120 Switching CharacteristicIeee 1149.1 Test Access Port Output Enable/Disable Output disable time tDIS is the difference betweenCapacitive Loading Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W Type Pins SwitchExample PinBottom View Ribbon Cable 3 0.1 inchesADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide