Analog Devices ADSP-21020 Dmpage, Dmts, Clkiin, Reset, Irq, FLAG3-0, Timexp, Rcomp, Evdd, Egnd

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ADSP-21020

Pin

 

 

 

 

Name

Type

Function

 

 

 

 

 

 

 

 

 

 

DMPAGE

O

Data Memory Page Boundary. The ADSP-

 

 

 

 

 

 

 

21020 asserts this pin to signal that a data

 

 

 

 

 

 

 

memory page boundary has been crossed.

 

 

 

 

 

 

 

Memory pages must be defined in the

 

 

 

 

 

 

 

memory control registers.

 

 

 

 

 

 

I/S

Data Memory Three-State Control.

 

 

DMTS

DMTS

 

 

 

 

 

 

 

places the data memory address, data,

 

 

 

 

 

 

 

selects, and strobes in a high-impedance

 

 

 

 

 

 

 

state. If DMTS is asserted while a DM

 

 

 

 

 

 

 

access is occurring, the processor will halt

 

 

 

 

 

 

 

and the memory access will not be

 

 

 

 

 

 

 

completed. DMACK must be asserted for

 

 

 

 

 

 

 

at least one cycle when DMTS is

 

 

 

 

 

 

 

deasserted to allow any pending memory

 

 

 

 

 

 

 

access to complete properly. DMTS should

 

 

 

 

 

 

 

only be asserted (low) during an active

 

 

 

 

 

 

 

memory access cycle.

CLKIIN

I

External clock input to the ADSP-21020.

 

 

 

 

 

 

 

The instruction cycle rate is equal to

 

 

 

 

 

 

 

CLKIN. CLKIN may not be halted,

 

 

 

 

 

 

 

changed, or operated below the specified

 

 

 

 

 

 

 

frequency.

 

 

 

 

 

I/A

Sets the ADSP-21020 to a known state and

RESET

 

 

 

 

 

 

 

begins execution at the program memory

 

 

 

 

 

 

 

location specified by the hardware reset

 

 

 

 

 

 

 

vector (address). This input must be

 

 

 

 

 

 

 

asserted (low) at power-up.

 

 

 

3–0

I/A

Interrupt request lines; may be either edge

IRQ

 

 

 

 

 

 

 

triggered or level-sensitive.

FLAG3–0

I/O/A

External Flags. Each is configured via

 

 

 

 

 

 

 

control bits as either an input or output. As

 

 

 

 

 

 

 

an input, it can be tested as a condition. As

 

 

 

 

 

 

 

an output, it can be used to signal external

 

 

 

 

 

 

 

peripherals.

 

 

 

I/A

Bus Request. Used by an external device to

BR

 

 

 

 

 

 

 

request control of the memory interface.

 

 

 

 

 

 

 

When BR is asserted, the processor halts

 

 

 

 

 

 

 

execution after completion of the current

 

 

 

 

 

 

 

cycle, places all memory data, addresses,

 

 

 

 

 

 

 

selects, and strobes in a high-impedance

 

 

 

 

 

 

 

state, and asserts BG. The processor

 

 

 

 

 

 

 

continues normal operation when BR is

 

 

 

 

 

 

 

released.

 

 

O

Bus Grant. Acknowledges a bus request

BG

 

 

 

 

 

 

 

(BR), indicating that the external device

 

 

 

 

 

 

 

may take control of the memory interface.

 

 

 

 

 

 

 

BG is asserted (held low) until BR is

 

 

 

 

 

 

 

released.

TIMEXP

O

Timer Expired. Asserted for four cycles

 

 

 

 

 

 

 

when the value of TCOUNT is

 

 

 

 

 

 

 

decremented to zero.

RCOMP

 

Compensation Resistor input. Controls

 

 

 

 

 

 

 

compensated output buffers. Connect

 

 

 

 

 

 

 

RCOMP through a 1.8 kΩ ± 15% resistor

 

 

 

 

 

 

 

to EVDD. Use of a capacitor (approxi-

 

 

 

 

 

 

 

mately 100 pF), placed in parallel with the

 

 

 

 

 

 

 

1.8 kΩ resistor is recommended.

EVDD

P

Power supply (for output drivers),

 

 

 

 

 

 

 

nominally +5 V dc (10 pins).

EGND

G

Power supply return (for output drivers);

 

 

 

 

 

 

 

(16 pins).

Pin

 

 

Name

Type

Function

 

 

 

 

IVDD

P

Power supply (for internal circuitry),

 

 

 

nominally +5 V dc (4 pins).

IGND

G

Power supply return (for internal circuitry); (7

 

 

 

pins).

TCK

I

Test Clock. Provides an asynchronous clock

 

 

 

for JTAG boundary scan.

TMS

I/S

Test Mode Select. Used to control the test

 

 

 

state machine. TMS has a 20 kΩ internal

 

 

 

pullup resistor.

TDI

VS

Test Data Input. Provides serial data for the

 

 

 

boundary scan logic. TDI has a 20 kΩ internal

 

 

 

pullup resistor.

TDO

O

Test Data Output. Serial scan output of the

 

 

 

boundary scan path.

 

 

I/A

Test Reset. Resets the test state machine.

TRST

 

 

 

TRST must be asserted (pulsed low) after

 

 

 

power-up or held low for proper operation of

 

 

 

the ADSP-21020. TRST has a 20 kΩ internal

 

 

 

pullup resistor.

NC

 

No Connect. No Connects are reserved pins

 

 

 

that must be left open and unconnected.

 

 

 

 

INSTRUCTION SET SUMMARY

The ADSP-21020 instruction set provides a wide variety of programming capabilities. Every instruction assembles into a single word and can execute in a single processor cycle. Multifunction instructions enable simultaneous multiplier and ALU operations, as well as computations executed in parallel with data transfers. The addressing power of the ADSP-21020 gives you flexibility in moving data both internally and externally. The ADSP-21020 assembly language uses an algebraic syntax for ease of coding and readability.

The instruction types are grouped into four categories: Compute and Move or Modify

Program Flow Control Immediate Move Miscellaneous

The instruction types are numbered; there are 22 types. Some instructions have more than one syntactical form; for example, Instruction 4 has four distinct forms. The instruction number itself has no bearing on programming, but corresponds to the opcode recognized by the ADSP-21020 device.

Because of the width and orthogonality of the instruction word, there are many possible instructions. For example, the ALU supports 21 fixed-point operations and 24 floating-point operations; each of these operations can be the compute portion of an instruction.

The following pages provide an overview and summary of the ADSP-21020 instruction set. For complete information, see the ADSP-21020 User’s Manual. For additional reference informa- tion, see the ADSP-21020 Programmer’s Quick Reference.

This section also contains several reference tables for using the instruction set.

Table I describes the notation and abbreviations used.

Table II lists all condition and termination code mnemonics.

Table III lists all register mnemonics.

Tables IV through VII list the syntax for all compute (ALU, multiplier, shifter or multifunction) operations.

Table VIII lists interrupts and their vector addresses.

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Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Dmts ResetDmpage ClkiinIf condition Compute ComputeIf condition DMIa, Mb = dregNotation Meaning ItalicsName Description Fixed-Point Floating-Point = MRB MRF = MRF = RND MRF = RND MRB MRF MRB = MRF= MRB MRF = MRF = SAT MRF = SAT MRB Shifter Shifter ImmediateIRQ3 Fixed-PointVector Address Hex Function IRQ2Grade Parameter Min Max Unit Parameter Test Conditions Min Max UnitClkin Period 150 Reset Setup before Clkin High 29 + DT/2Timing Requirement Clkin Width HighHold after Clkin High Pulse Width TCK +TDTEX Clkin High to Timexp Clkin High to FLAG3-0OUTEnable FLAG3-0INSetup before Clkin High 19 + 5DT/16FLAG3-0OUTDelay from Clkin High Clkin High to FLAG3-0OUTDisableTiming Requirement Memory Interface Disable to LowClkin High to Memory Interface Enable 25 + DT/2 Hold after Clkin HighXTS Delay after Setup before Clkin High 14 + DT/4XTS Delay after Address, Select 28 + 7DT/8 Low 16 + DT/2 Switching CharacteristicXACK Setup before Clkin High + DT/4 XACK Delay from Address + 7DT/8XACK Delay from XRD Low + DT/2 XACK Hold after Clkin High Switching CharacteristicMemory Read Data Setup before XWR High + DT/2 XACK Delay from Address, Select 27 + 7DT/8XACK Delay from XWR Low 15 + DT/2 Data Disable before XWR XRD Low + 3DT/8Memory Write Pulse Width 200 160 132 120 Switching Characteristic TDI, TMS Setup before TCK HighSystem Inputs Setup before TCK High TDO Delay from TCK LowIeee 1149.1 Test Access Port Output disable time tDIS is the difference between Output Enable/DisableCapacitive Loading Pin Type Pins SwitchExample Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W3 0.1 inches Bottom View Ribbon CableADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide