Analog Devices ADSP-21020 manual Setup before Clkin High 14 + DT/4, Xts, XTS Delay after

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ADSP-21020

External Memory Three-State Control

K/B/T Grade

K/B/T Grade

B/T Grade

K Grade

20 MHz

25 MHz

30 MHz

33.3 MHz

Frequency Dependency*

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirement:

tSTS

, Setup before CLKIN High

14

50

12

40

10

33

9

30

14 + DT/4

tCK

ns

xTS

tDADTS

xTS

Delay after Address, Select

28

19

13

10

28 + 7DT/8

ns

tDSTS

xTS

Delay after

XRD

,

XWR

Low

16

11

7

6

16 + DT/2

ns

Switching Characteristic:

tDTSD

Memory Interface Disable before

CLKIN High

0

–2

–4

–5

DT/4

ns

tDTSAE

High to Address, Select Enable

0

0

0

0

ns

xTS

NOTES

*DT = tCK – 50 ns.

xTS should only be asserted (low) during an active memory access cycle.

Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE. Address = PMA23-0, DMA31-0. Select = PMS1-0, DMS3-0.

x = PM or DM.

CLKIN

tSTS

tSTS

PMTS, DMTS

tDADTS

t DSTS

tDTSD

xRD, xWR

t DTSAE

ADDRESS,

SELECTS

DATA

Figure 9. External Memory Three-State Control

REV. C

–17–

Image 17

Contents ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Dmpage ResetDmts ClkiinIf condition ComputeIf condition Compute DMIa, Mb = dregName Description Notation MeaningItalics Fixed-Point Floating-Point = MRB MRF = MRF = SAT MRF = SAT MRB MRF MRB = MRF= MRB MRF = MRF = RND MRF = RND MRB Shifter Shifter ImmediateVector Address Hex Function Fixed-PointIRQ3 IRQ2Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitTiming Requirement Reset Setup before Clkin High 29 + DT/2Clkin Period 150 Clkin Width HighTDTEX Clkin High to Timexp Hold after Clkin HighPulse Width TCK + FLAG3-0OUTDelay from Clkin High FLAG3-0INSetup before Clkin High 19 + 5DT/16Clkin High to FLAG3-0OUTEnable Clkin High to FLAG3-0OUTDisableClkin High to Memory Interface Enable 25 + DT/2 Memory Interface Disable to LowTiming Requirement Hold after Clkin HighXTS Delay after Address, Select 28 + 7DT/8 Setup before Clkin High 14 + DT/4XTS Delay after Low 16 + DT/2 Switching CharacteristicXACK Delay from XRD Low + DT/2 XACK Delay from Address + 7DT/8XACK Setup before Clkin High + DT/4 XACK Hold after Clkin High Switching CharacteristicMemory Read XACK Delay from XWR Low 15 + DT/2 XACK Delay from Address, Select 27 + 7DT/8Data Setup before XWR High + DT/2 Data Disable before XWR XRD Low + 3DT/8Memory Write System Inputs Setup before TCK High TDI, TMS Setup before TCK HighPulse Width 200 160 132 120 Switching Characteristic TDO Delay from TCK LowIeee 1149.1 Test Access Port Output Enable/Disable Output disable time tDIS is the difference betweenCapacitive Loading Example Type Pins SwitchPin Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 WBottom View Ribbon Cable 3 0.1 inchesADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide