Cypress CY7C1357C, CY7C1355C Scan Register Sizes, Identification Codes, Register Name Bit Size

Page 15

 

 

 

 

CY7C1355C

 

 

 

 

CY7C1357C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Scan Register Sizes

 

 

 

 

 

 

Register Name

Bit Size (x36)

Bit Size (x18)

 

 

 

 

Instruction

3

3

 

 

 

 

 

Bypass

1

1

 

 

 

 

 

ID

32

32

 

 

 

 

 

Boundary Scan Order (119-ball BGA package)

69

69

 

 

 

 

 

Boundary Scan Order (165-ball FBGA package)

69

69

 

 

 

 

 

 

 

Identification Codes

Instruction

Code

Description

EXTEST

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and

 

 

TDO. This operation does not affect SRAM operations.

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOAD

100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

Does not affect SRAM operation. This instruction does not implement 1149.1 preload

 

 

function and is therefore not 1149.1 compliant.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

operations.

Document #: 38-05539 Rev. *E

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Contents 133 MHz 100 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1357C 512K x Logic Block Diagram CY7C1355C 256K xCY7C1355C Pin Configurations Pin Tqfp PinoutCY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag Pin Configurations Ball Fbga Pinout 3 Chip enable with Jtag CE2 CLKCE2 Name Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Pin DefinitionsFunctional Overview Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1355C Sleep ModePartial Truth Table for Read/Write2, 3 Truth Table for Read/Write2, 3,9TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Description Min Max Unit Clock Output TimesIdentification Register Definitions 3V TAP AC Test Conditions5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeName CY7C1355C 256K x Bit# Ball ID SignalCY7C1357C 512K x Bit# Ball Id Signal Name Ball BGA Boundary Scan OrderCY7C1355C 256K x Bit# Ball ID Signal Name Ball Fbga Boundary Scan OrderBWD Ambient Range Electrical Characteristics Over the Operating Range13Maximum Ratings Operating Range3V I/O Test Load Capacitance15Thermal Resistance15 AC Test Loads and Waveforms100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 16Write Switching WaveformsCommand Read/Write Waveforms22, 23QA4+1 DA5 QA6 DA7 NOP, Stall and Deselect Cycles22, 23ZZ Mode Timing26 Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball BGA 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change