Cypress CY7C1355C, CY7C1357C manual Document History, Issue Date Orig. Description of Change

Page 28

CY7C1355C

CY7C1357C

Document History Page

Document Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture

Document Number: 38-05539

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

242032

See ECN

RKF

New data sheet

 

 

 

 

 

*A

332059

See ECN

PCI

Changed Boundary Scan Order to match the B rev of these devices

 

 

 

 

Removed description on Extest Output Bus Tri-state

 

 

 

 

Removed 117 MHz Speed Bin

 

 

 

 

Changed IDDZZ from 35 mA to 50 mA on Pg # 9

 

 

 

 

Changed ISB1 and ISB3 from 40 mA to 110 and 100 mA respectively

 

 

 

 

Address expansion pins/balls in the pinouts for all packages are modified as

 

 

 

 

per JEDEC standard

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Corrected ISB4 Test Condition from (VIN ≥ VDD – 0.3V or VIN ≤ 0.3V) to (VIN ≥ VIH

 

 

 

 

or VIN ≤ VIL) in the Electrical Characteristic Table on Pg #18

 

 

 

 

Changed ΘJA and ΘJc for TQFP Package from 25 and 9 °C/W to 29.41 and

 

 

 

 

6.13 °C/W

 

 

 

 

respectively

 

 

 

 

Changed ΘJA and ΘJc for BGA Package from 25 and 6 °C/W to 34.1 and 14.0

 

 

 

 

°C/W

 

 

 

 

respectively

 

 

 

 

Changed ΘJA and ΘJc for FBGA Package from 27 and 6 °C/W to 16.8 and 3.0

 

 

 

 

°C/W respectively

 

 

 

 

Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA

 

 

 

 

Packages

 

 

 

 

Updated Ordering Information Table

 

 

 

 

Changed from Preliminary to Final

*B

351895

See ECN

PCI

Changed ISB2 from 30 to 40 mA

 

 

 

 

Updated Ordering Information Table

*C

377095

See ECN

PCI

Modified test condition in note# 14 from VIH < VDD to VIH < VDD

*D

408298

See ECN

RXU

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

 

 

 

 

Electrical Characteristics Table

 

 

 

 

Changed three-state to tri-state

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

 

 

 

 

Updated Ordering Information Table

*E

501793

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

 

 

 

 

Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

Document #: 38-05539 Rev. *E

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Contents Features Functional Description1Selection Guide 133 MHz 100 MHz UnitLogic Block Diagram CY7C1355C 256K x Logic Block Diagram CY7C1357C 512K xPin Configurations Pin Tqfp Pinout CY7C1355CCY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag CE2 CLK Pin Configurations Ball Fbga Pinout 3 Chip enable with JtagCE2 Power supply inputs to the core of the device Power supply for the I/O circuitryPin Definitions Name DescriptionSingle Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Sleep Mode Partial Truth Table for Read/Write2, 3Truth Table for Read/Write2, 3,9 Function CY7C1355CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up Times3V TAP AC Test Conditions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionCY7C1355C 256K x Bit# Ball ID Signal CY7C1357C 512K x Bit# Ball Id Signal NameBall BGA Boundary Scan Order NameBall Fbga Boundary Scan Order CY7C1355C 256K x Bit# Ball ID Signal NameBWD Electrical Characteristics Over the Operating Range13 Maximum RatingsOperating Range Ambient RangeCapacitance15 Thermal Resistance15AC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range 16 100 Parameter Description Unit Min MaxSwitching Waveforms CommandRead/Write Waveforms22, 23 WriteNOP, Stall and Deselect Cycles22, 23 QA4+1 DA5 QA6 DA7ZZ Mode Timing26 Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History
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