Cypress CY7C1355C, CY7C1357C manual Switching Characteristics Over the Operating Range 16

Page 20

CY7C1355C

CY7C1357C

Switching Characteristics Over the Operating Range [16, 17]

 

 

 

 

 

 

 

 

 

 

–133

 

 

–100

 

Parameter

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

Min.

 

Max.

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

tPOWER

 

VDD(Typical) to the First Access[18]

1

 

 

1

 

 

ms

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

 

Clock Cycle Time

7.5

 

 

10

 

 

ns

tCH

 

Clock HIGH

3.0

 

 

4.0

 

 

ns

tCL

 

Clock LOW

3.0

 

 

4.0

 

 

ns

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCDV

 

Data Output Valid after CLK Rise

 

 

6.5

 

 

7.5

ns

tDOH

 

Data Output Hold after CLK Rise

2.0

 

 

2.0

 

 

ns

t

 

Clock to Low-Z[19, 20, 21]

0

 

 

0

 

 

ns

CLZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

 

Clock to High-Z[19, 20, 21]

 

 

3.5

 

 

3.5

ns

CHZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOEV

 

 

 

LOW to Output Valid

 

 

3.5

 

 

3.5

ns

OE

 

 

 

t

 

 

 

LOW to Output Low-Z[19, 20, 21]

0

 

 

0

 

 

ns

OE

 

 

 

OELZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOEHZ

 

 

 

HIGH to Output High-Z[19, 20, 21]

 

 

3.5

 

 

3.5

ns

OE

 

 

 

Set-up Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

 

Address Set-up before CLK Rise

1.5

 

 

1.5

 

 

ns

tALS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV/LD

 

Set-up before CLK Rise

1.5

 

 

1.5

 

 

ns

tWES

 

 

 

 

 

 

 

 

X Set-up before CLK Rise

1.5

 

 

1.5

 

 

ns

WE,

BW

 

 

 

tCENS

 

 

 

 

Set-up before CLK Rise

1.5

 

 

1.5

 

 

ns

CEN

 

 

 

tDS

 

Data Input Set-up before CLK Rise

1.5

 

 

1.5

 

 

ns

tCES

 

Chip Enable Set-Up before CLK Rise

1.5

 

 

1.5

 

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

 

Address Hold after CLK Rise

0.5

 

 

0.5

 

 

ns

tALH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV/LD

Hold after CLK Rise

0.5

 

 

0.5

 

 

ns

tWEH

 

 

 

 

 

 

 

X Hold after CLK Rise

0.5

 

 

0.5

 

 

ns

WE,

BW

 

 

 

tCENH

 

 

 

 

Hold after CLK Rise

0.5

 

 

0.5

 

 

ns

CEN

 

 

 

tDH

 

Data Input Hold after CLK Rise

0.5

 

 

0.5

 

 

ns

tCEH

 

Chip Enable Hold after CLK Rise

0.5

 

 

0.5

 

 

ns

Notes:

16.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

18.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a Read or Write operation can be initiated.

19.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

20.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

21.This parameter is sampled and not 100% tested.

Document #: 38-05539 Rev. *E

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Contents Features Functional Description1Selection Guide 133 MHz 100 MHz UnitLogic Block Diagram CY7C1355C 256K x Logic Block Diagram CY7C1357C 512K xPin Configurations Pin Tqfp Pinout CY7C1355CCY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag CE2 Pin Configurations Ball Fbga Pinout 3 Chip enable with JtagCE2 CLK Power supply inputs to the core of the device Power supply for the I/O circuitryPin Definitions Name DescriptionSingle Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Sleep Mode Partial Truth Table for Read/Write2, 3Truth Table for Read/Write2, 3,9 Function CY7C1355CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram Bypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up Times3V TAP AC Test Conditions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionCY7C1355C 256K x Bit# Ball ID Signal CY7C1357C 512K x Bit# Ball Id Signal NameBall BGA Boundary Scan Order NameBWD CY7C1355C 256K x Bit# Ball ID Signal NameBall Fbga Boundary Scan Order Electrical Characteristics Over the Operating Range13 Maximum RatingsOperating Range Ambient RangeCapacitance15 Thermal Resistance15AC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range 16 100 Parameter Description Unit Min MaxSwitching Waveforms CommandRead/Write Waveforms22, 23 WriteNOP, Stall and Deselect Cycles22, 23 QA4+1 DA5 QA6 DA7ZZ Mode Timing26 Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History
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