Cypress CY7C1355C manual Partial Truth Table for Read/Write2, 3, Truth Table for Read/Write2, 3,9

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CY7C1355C

CY7C1357C

Truth Table[2, 3, 4, 5, 6, 7, 8]

Address

Operation

Used

CE

1

CE2

CE

3

ZZ

ADV/LD

WE

BWX

OE

CEN

CLK

DQ

NOP/WRITE ABORT (Begin Burst)

None

L

H

L

L

L

L

H

X

L

L->H

Tri-State

WRITE ABORT (Continue Burst)

Next

X

X

X

L

H

X

H

X

L

L->H

Tri-State

IGNORE CLOCK EDGE (Stall)

Current

X

X

X

L

X

X

X

X

H

L->H

–

SLEEP MODE

None

X

X

X

H

X

X

X

X

X

X

Tri-State

Partial Truth Table for Read/Write[2, 3, 9]

Function (CY7C1355C)

WE

BWA

BWB

BWC

BWD

Read

H

X

X

X

X

Write No bytes written

L

H

H

H

H

Write Byte A – (DQA and DQPA)

L

L

H

H

H

Write Byte B – (DQB and DQPB)

L

H

L

H

H

Write Byte C – (DQC and DQPC)

L

H

H

L

H

Write Byte D – (DQD and DQPD)

L

H

H

H

L

Write All Bytes

L

L

L

L

L

Truth Table for Read/Write[2, 3,9]


Function (CY7C1357C)		WE			BWA			BWB
Read		H			X			X

Write - No bytes written		L			H			H

Write Byte A – (DQA and DQPA)		L			H			H
Write Byte B – (DQB and DQPB)		L			H			H
Write All Bytes		L			L			L

Note:

9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.

Document #: 38-05539 Rev. *E

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Contents Selection Guide FeaturesFunctional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1355C 256K x Logic Block Diagram CY7C1357C 512K xPin Configurations Pin Tqfp Pinout CY7C1355CCY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag CE2 CLK Pin Configurations Ball Fbga Pinout 3 Chip enable with JtagCE2 Pin Definitions Power supply inputs to the core of the devicePower supply for the I/O circuitry Name DescriptionSingle Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Truth Table for Read/Write2, 3,9 Sleep ModePartial Truth Table for Read/Write2, 3 Function CY7C1355CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times5V TAP AC Output Load Equivalent 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBall BGA Boundary Scan Order CY7C1355C 256K x Bit# Ball ID SignalCY7C1357C 512K x Bit# Ball Id Signal Name NameBall Fbga Boundary Scan Order CY7C1355C 256K x Bit# Ball ID Signal NameBWD Operating Range Electrical Characteristics Over the Operating Range13Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance15Thermal Resistance15 3V I/O Test LoadSwitching Characteristics Over the Operating Range 16 100 Parameter Description Unit Min MaxRead/Write Waveforms22, 23 Switching WaveformsCommand WriteNOP, Stall and Deselect Cycles22, 23 QA4+1 DA5 QA6 DA7ZZ Mode Timing26 Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History