Cypress CY7C1355C, CY7C1357C manual NOP, Stall and Deselect Cycles22, 23, QA4+1 DA5 QA6 DA7

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CY7C1355C

CY7C1357C

Switching Waveforms (continued)

NOP, STALL and DESELECT Cycles[22, 23, 25]

1

2

tCYC 3

4

5

6

7

8

9

10

CLK

 

 

 

 

 

 

 

 

 

tCENS tCENH

tCH

tCL

 

 

 

 

 

 

 

CEN

tCES tCEH

CE

ADV/LD

WE

BWX

ADDRESS

A1

A2

 

A3

A4

 

A5

A6

A7

 

tAS

tAH

 

 

tCDV

 

 

 

 

 

 

 

 

tCLZ

tDOH

tOEV tCHZ

 

 

 

 

 

 

 

 

 

 

DQ

 

D(A1)

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6)

D(A7)

 

tDS

tDH

 

 

 

tOEHZ

tDOH

 

 

 

OE

 

 

 

 

 

 

tOELZ

 

 

 

COMMAND

WRITE

WRITE

BURST

READ

READ

BURST

WRITE

READ

WRITE

DESELECT

 

 

D(A1)

D(A2)

WRITE

Q(A3)

Q(A4)

READ

D(A5)

Q(A6)

D(A7)

 

 

 

 

D(A2+1)

 

 

Q(A4+1)

 

 

 

 

 

 

 

 

DON’T CARE

UNDEFINED

 

 

 

Note:

25. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.

Document #: 38-05539 Rev. *E

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Contents Selection Guide FeaturesFunctional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1355C 256K x Logic Block Diagram CY7C1357C 512K xPin Configurations Pin Tqfp Pinout CY7C1355CCY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag CE2 CLK Pin Configurations Ball Fbga Pinout 3 Chip enable with JtagCE2 Pin Definitions Power supply inputs to the core of the devicePower supply for the I/O circuitry Name DescriptionSingle Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Truth Table for Read/Write2, 3,9 Sleep ModePartial Truth Table for Read/Write2, 3 Function CY7C1355CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times5V TAP AC Output Load Equivalent 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBall BGA Boundary Scan Order CY7C1355C 256K x Bit# Ball ID SignalCY7C1357C 512K x Bit# Ball Id Signal Name NameBall Fbga Boundary Scan Order CY7C1355C 256K x Bit# Ball ID Signal NameBWD Operating Range Electrical Characteristics Over the Operating Range13Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance15Thermal Resistance15 3V I/O Test LoadSwitching Characteristics Over the Operating Range 16 100 Parameter Description Unit Min MaxRead/Write Waveforms22, 23 Switching WaveformsCommand WriteNOP, Stall and Deselect Cycles22, 23 QA4+1 DA5 QA6 DA7ZZ Mode Timing26 Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History