Cypress manual Logic Block Diagram CY7C1355C 256K x, Logic Block Diagram CY7C1357C 512K x

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										CY7C1355C
										CY7C1357C
1
Logic Block Diagram – CY7C1355C (256K x 36)
	A0, A1, A	ADDRESS	A1			A1'
	A0, A1, A	REGISTER
		REGISTER		D1	Q1
	MODE		A0	D0	Q0	A0'
		CE	ADV/LD		BURST
CLK	C	CE			LOGIC
CLK	C				LOGIC
CEN			C
			WRITE ADDRESS
			REGISTER							O
										O
										U
										T
								S	D	P
								S	A	U
								E	T	T
	ADV/LD							N	A
	BWA						MEMORY	S		B
	BWA		WRITE REGISTRY			WRITE	ARRAY	E	S	U	DQs
			WRITE REGISTRY			WRITE	ARRAY	E	S	U	DQs
	BWB		AND DATA COHERENCY			DRIVERS		A	T	F	DQPA
	BWC		CONTROL LOGIC					A	E	F	DQPB
			CONTROL LOGIC					M	E	F	DQPB
								M	E	E	DQPC
	BWD							P	R	R	DQPC
								P	R	R	DQPD
								S	I	S
								S	I	S
	WE								N		E
									G
							INPUT	E
	OE						REGISTER	E
	OE	READ LOGIC
	CE1	READ LOGIC
	CE1
	CE2
	CE3		SLEEP
	ZZ		SLEEP
	ZZ	CONTROL
		CONTROL
2
Logic Block Diagram – CY7C1357C (512K x 18)

	A0, A1, A	ADDRESS	A1			A1'
	A0, A1, A	REGISTER
		REGISTER		D1	Q1
	MODE		A0	D0	Q0	A0'
		CE	ADV/LD		BURST
CLK	C	CE			LOGIC
CLK	C				LOGIC
CEN			C
			WRITE ADDRESS
			REGISTER
								S	D
								S	A
								E	T
	ADV/LD							N	A
	BWA						MEMORY	S
	BWA		WRITE REGISTRY			WRITE	ARRAY	E	S
			WRITE REGISTRY			WRITE	ARRAY	E	S
	BWB		AND DATA COHERENCY			DRIVERS		A	T
			CONTROL LOGIC					A	E
								M	E
								P	R
	WE							S	I
	WE								N
									G
							INPUT	E
	OE						REGISTER	E
	OE	READ LOGIC
	CE1	READ LOGIC
	CE1
	CE2
	CE3
	ZZ	SLEEP
		CONTROL

DQs

DQPA DQPB

Document #: 38-05539 Rev. *E

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Contents Selection Guide FeaturesFunctional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1355C 256K x Logic Block Diagram CY7C1357C 512K xPin Configurations Pin Tqfp Pinout CY7C1355CCY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag CE2 Pin Configurations Ball Fbga Pinout 3 Chip enable with JtagCE2 CLK Pin Definitions Power supply inputs to the core of the devicePower supply for the I/O circuitry Name DescriptionSingle Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Truth Table for Read/Write2, 3,9 Sleep ModePartial Truth Table for Read/Write2, 3 Function CY7C1355CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram Bypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times5V TAP AC Output Load Equivalent 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBall BGA Boundary Scan Order CY7C1355C 256K x Bit# Ball ID SignalCY7C1357C 512K x Bit# Ball Id Signal Name NameBWD CY7C1355C 256K x Bit# Ball ID Signal NameBall Fbga Boundary Scan Order Operating Range Electrical Characteristics Over the Operating Range13Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance15Thermal Resistance15 3V I/O Test LoadSwitching Characteristics Over the Operating Range 16 100 Parameter Description Unit Min MaxRead/Write Waveforms22, 23 Switching WaveformsCommand WriteNOP, Stall and Deselect Cycles22, 23 QA4+1 DA5 QA6 DA7ZZ Mode Timing26 Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History

CY7C1357C

Logic Block Diagram – CY7C1355C (256K x 36)

Logic Block Diagram – CY7C1357C (512K x 18)