Cypress CY7C1357C, CY7C1355C manual Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag

Page 5

CY7C1355C

CY7C1357C

Pin Configurations (continued)

119-Ball BGA Pinout (3 Chip Enables with JTAG)

CY7C1355C (256K x 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

NC/18M

A

A

VDDQ

B

NC/576M

CE2

A

A

ADV/LD

CE

3

NC

C

NC/1G

A

A

VDD

A

A

NC

D

DQC

DQPC

VSS

NC

VSS

DQPB

DQB

E

DQC

DQC

VSS

1

VSS

DQB

DQB

CE

F

VDDQ

DQC

VSS

VSS

DQB

VDDQ

OE

G

DQC

DQC

C

A

B

DQB

DQB

BW

BW

H

DQC

DQC

VSS

VSS

DQB

DQB

WE

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD

DQD

VSS

CLK

VSS

DQA

DQA

L

DQD

DQD

D

NC

A

DQA

DQA

BW

BW

M

VDDQ

DQD

VSS

VSS

DQA

VDDQ

CEN

N

DQD

DQD

VSS

A1

VSS

DQA

DQA

P

DQD

DQPD

VSS

A0

VSS

DQPA

DQA

R

NC/144M

A

MODE

VDD

NC

A

NC/288M

T

NC

NC/72M

A

A

A

NC/36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1357C (512K x 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

NC/18M

A

A

VDDQ

B

NC/576M

CE2

A

A

NC

ADV/LD

CE

3

C

NC/1G

A

A

VDD

A

A

NC

D

DQB

NC

VSS

NC

VSS

DQPA

NC

E

NC

DQB

VSS

1

VSS

NC

DQA

CE

F

VDDQ

NC

VSS

VSS

DQA

VDDQ

OE

G

NC

DQB

B

A

VSS

NC

DQA

BW

H

DQB

NC

VSS

VSS

DQA

NC

WE

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB

VSS

CLK

VSS

NC

DQA

L

DQB

NC

VSS

NC

A

DQA

NC

BW

M

VDDQ

DQB

VSS

VSS

NC

VDDQ

CEN

N

DQB

NC

VSS

A1

VSS

DQA

NC

P

NC

DQPB

VSS

A0

VSS

NC

DQA

R

NC/144M

A

MODE

VDD

NC

A

NC/288M

T

NC/72M

A

A

NC/36M

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document #: 38-05539 Rev. *E

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Contents Functional Description1 FeaturesSelection Guide 133 MHz 100 MHz UnitLogic Block Diagram CY7C1357C 512K x Logic Block Diagram CY7C1355C 256K xCY7C1355C Pin Configurations Pin Tqfp PinoutCY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag CE2 Pin Configurations Ball Fbga Pinout 3 Chip enable with JtagCE2 CLK Power supply for the I/O circuitry Power supply inputs to the core of the devicePin Definitions Name DescriptionBurst Read Accesses Single Read AccessesSingle Write Accesses Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Partial Truth Table for Read/Write2, 3 Sleep ModeTruth Table for Read/Write2, 3,9 Function CY7C1355CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram TAP Instruction Set Bypass RegisterParameter Description Min Max Unit Clock TAP TimingOutput Times Set-up Times5V TAP AC Test Conditions 3V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Register DefinitionsIdentification Codes Scan Register SizesRegister Name Bit Size Instruction Code DescriptionCY7C1357C 512K x Bit# Ball Id Signal Name CY7C1355C 256K x Bit# Ball ID SignalBall BGA Boundary Scan Order NameBWD CY7C1355C 256K x Bit# Ball ID Signal NameBall Fbga Boundary Scan Order Maximum Ratings Electrical Characteristics Over the Operating Range13Operating Range Ambient RangeThermal Resistance15 Capacitance15AC Test Loads and Waveforms 3V I/O Test Load100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 16Command Switching WaveformsRead/Write Waveforms22, 23 WriteQA4+1 DA5 QA6 DA7 NOP, Stall and Deselect Cycles22, 23ZZ Mode Timing26 Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball BGA 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change