Cypress CY7C1357C TAP Timing, Parameter Description Min Max Unit Clock, Output Times, Hold Times

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CY7C1355C

CY7C1357C

TAP Timing

12

Test Clock

(TCK)tTH

tTMSS tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3

4

5

6

tTL tCYC

tTDOV

tTDOX

 

Test Data-Out

 

 

 

 

(TDO)

 

 

 

 

DON’T CARE

UNDEFINED

 

 

TAP AC Switching Characteristics Over the Operating Range[10, 11]

 

 

Parameter

Description

Min.

Max.

Unit

Clock

 

 

 

 

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH Time

20

 

ns

tTL

TCK Clock LOW Time

20

 

ns

Output Times

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

Set-up Times

 

 

 

tTMSS

TMS Set-Up to TCK Clock Rise

5

 

ns

tTDIS

TDI Set-Up to TCK Clock Rise

5

 

ns

tCS

Capture Set-Up to TCK Rise

5

 

ns

Hold Times

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Notes:

10.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

11.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Document #: 38-05539 Rev. *E

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Contents Functional Description1 FeaturesSelection Guide 133 MHz 100 MHz UnitLogic Block Diagram CY7C1357C 512K x Logic Block Diagram CY7C1355C 256K xCY7C1355C Pin Configurations Pin Tqfp PinoutCY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag CE2 CLK Pin Configurations Ball Fbga Pinout 3 Chip enable with JtagCE2 Power supply for the I/O circuitry Power supply inputs to the core of the devicePin Definitions Name DescriptionBurst Read Accesses Single Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Partial Truth Table for Read/Write2, 3 Sleep ModeTruth Table for Read/Write2, 3,9 Function CY7C1355CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterParameter Description Min Max Unit Clock TAP TimingOutput Times Set-up Times5V TAP AC Test Conditions 3V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Register DefinitionsIdentification Codes Scan Register SizesRegister Name Bit Size Instruction Code DescriptionCY7C1357C 512K x Bit# Ball Id Signal Name CY7C1355C 256K x Bit# Ball ID SignalBall BGA Boundary Scan Order NameBall Fbga Boundary Scan Order CY7C1355C 256K x Bit# Ball ID Signal NameBWD Maximum Ratings Electrical Characteristics Over the Operating Range13Operating Range Ambient RangeThermal Resistance15 Capacitance15AC Test Loads and Waveforms 3V I/O Test Load100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 16Command Switching WaveformsRead/Write Waveforms22, 23 WriteQA4+1 DA5 QA6 DA7 NOP, Stall and Deselect Cycles22, 23ZZ Mode Timing26 Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball BGA 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change