Cypress CY7C1355C, CY7C1357C Pin Configurations Ball Fbga Pinout 3 Chip enable with Jtag, CE2 CLK

Page 6

CY7C1355C

CY7C1357C

Pin Configurations (continued)

165-Ball FBGA Pinout (3 Chip enable with JTAG)

CY7C1355C (256K x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/576M

1

C

B

3

A

CE

BW

BW

CE

CEN

ADV/LD

A

A

NC

B

NC/1G

A

CE2

D

A

CLK

NC/18M

A

NC

BW

BW

WE

OE

C

DQPC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DQPB

D

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

E

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

F

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

G

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

K

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

L

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

M

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

N

DQPD

NC

VDDQ

VSS

NC

NC

NC

VSS

VDDQ

NC

DQPA

P

NC/144M

NC/72M

A

A

TDI

A1

TDO

A

A

A

NC/288M

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

CY7C1357C (512K x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/576M

1

B

NC

3

A

A

A

A

CE

BW

CE

CEN

ADV/LD

B

NC/1G

A

CE2

NC

A

CLK

NC/18M

A

NC

BW

WE

OE

C

NC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DQPA

D

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

E

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

F

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

G

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

K

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

L

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

M

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

N

DQPB

NC

VDDQ

VSS

NC

NC

NC

VSS

VDDQ

NC

NC

P

NC/144M

NC/72M

A

A

TDI

A1

TDO

A

A

A

NC/288M

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

Document #: 38-05539 Rev. *E

Page 6 of 28

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Contents Selection Guide FeaturesFunctional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1355C 256K x Logic Block Diagram CY7C1357C 512K xPin Configurations Pin Tqfp Pinout CY7C1355CCY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag Pin Configurations Ball Fbga Pinout 3 Chip enable with Jtag CE2 CLKCE2 Pin Definitions Power supply inputs to the core of the devicePower supply for the I/O circuitry Name DescriptionSingle Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Truth Table for Read/Write2, 3,9 Sleep ModePartial Truth Table for Read/Write2, 3 Function CY7C1355CTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times5V TAP AC Output Load Equivalent 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBall BGA Boundary Scan Order CY7C1355C 256K x Bit# Ball ID SignalCY7C1357C 512K x Bit# Ball Id Signal Name NameCY7C1355C 256K x Bit# Ball ID Signal Name Ball Fbga Boundary Scan OrderBWD Operating Range Electrical Characteristics Over the Operating Range13Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance15Thermal Resistance15 3V I/O Test LoadSwitching Characteristics Over the Operating Range 16 100 Parameter Description Unit Min MaxRead/Write Waveforms22, 23 Switching WaveformsCommand WriteNOP, Stall and Deselect Cycles22, 23 QA4+1 DA5 QA6 DA7ZZ Mode Timing26 Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History