Cypress CY7C1371D, CY7C1373D manual Ieee 1149.1 Serial Boundary Scan Jtag

CY7C1371D

CY7C1373D

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1371D/CY7C1373D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels.

The CY7C1371D/CY7C1373D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are inter- nally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device is up in a reset state which does not interfere with the operation of the device.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller State Diagram

TAP Controller Block Diagram

1

0

TEST-LOGIC

RESET

0

RUN-TEST/

IDLE

1	SELECT		1	SELECT
	DR-SCAN			IR-SCAN
		0			0
	1			1
	CAPTURE-DR			CAPTURE-IR
		0			0
	SHIFT-DR		0	SHIFT-IR
		1			1
	EXIT1-DR		1	EXIT1-IR
		0			0
	PAUSE-DR		0	PAUSE-IR
		1			1
	0			0
	EXIT2-DR			EXIT2-IR
		1			1
	UPDATE-DR			UPDATE-IR
	1	0		1	0

1

0

1

0

												0
					Bypass Register
	Selection									2	1	0	Selection
TDI			Instruction					Register						TDO
	Circuitry												Circuitry
			31	30	29	.	.		.	2	1	0
		Identification						Register
			x	.	.	.	.		.	2	1	0
		Boundary Scan Register

TCK

TAP CONTROLLER

TMS

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE

Document #: 38-05556 Rev. *F Page 11 of 29

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