Cypress CY7C1371D, CY7C1373D manual Interleaved Burst Address Table Mode = Floating or VDD

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CY7C1371D

CY7C1373D

details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle.

The data written during the Write operation is controlled by BWX signals. The CY7C1371D/CY7C1373D provides byte write capability that is described in the truth table. Asserting the Write Enable input (WE) with the selected Byte Write Select input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remains unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations.

Because the CY7C1371D/CY7C1373D is a common IO device, data must not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQPX inputs. Doing so tri-states the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1371D/CY7C1373D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWX inputs must be driven in each cycle of the burst write, to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table (MODE = Floating or VDD)

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

 

 

 

 

01

00

11

10

 

 

 

 

10

11

00

01

 

 

 

 

11

10

01

00

 

 

 

 

Linear Burst Address Table (MODE = GND)

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

 

 

 

 

01

10

11

00

 

 

 

 

10

11

00

01

 

 

 

 

11

00

01

10

 

 

 

 

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

 

 

 

 

 

 

IDDZZ

Sleep mode standby current

ZZ > VDD – 0.2V

 

80

mA

tZZS

Device operation to ZZ

ZZ > VDD – 0.2V

 

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2V

2tCYC

 

ns

tZZI

ZZ active to sleep current

This parameter is sampled

 

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

 

ns

Document #: 38-05556 Rev. *F

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Contents Selection Guide Functional Description1 Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1373D 1M x Logic Block Diagram CY7C1371D 512K xCY7C1371D Pin Configurations Pin Tqfp PinoutCY7C1373D Pin Configurations CE2 Pin Configurations Ball Fbga PinoutPin Definitions Burst Read Accesses Single Read AccessesSingle Write Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Address Operation Used Partial Truth Table for Read/Write 2, 3Function CY7C1371D Function CY7C1373DIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State Diagram TAP Controller Block DiagramTAP Instruction Set Bypass RegisterExtest Output Bus Tri-State TAP TimingSetup Times TAP AC Switching Characteristics Over the Operating Range10Parameter Description Min Max Unit Clock Output TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test ConditionsParameter Description Conditions Min Max Unit Scan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 13A10 B10 P10 Maximum Ratings Electrical CharacteristicsOperating Range Ambient RangeCapacitance18 Thermal Resistance18AC Test Loads and Waveforms 133 MHz 100 MHz Parameter Description Unit Min Max Switching Characteristics Over the Operating Range23Read/Write Waveforms25, 26 Switching WaveformsRite ReadAddress NOP, Stall and Deselect Cycles25, 26Stall Stall NOPDON’T Care ZZ Mode Timing29Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History Issue Orig. Description of Change Date