Linear Burst Address Table Mode = GND | Cypress CY7C1371D guide

CY7C1371D

CY7C1373D

details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle.

The data written during the Write operation is controlled by BWX signals. The CY7C1371D/CY7C1373D provides byte write capability that is described in the truth table. Asserting the Write Enable input (WE) with the selected Byte Write Select input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remains unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations.

Because the CY7C1371D/CY7C1373D is a common IO device, data must not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQPX inputs. Doing so tri-states the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1371D/CY7C1373D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWX inputs must be driven in each cycle of the burst write, to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table (MODE = Floating or VDD)

First	Second	Third	Fourth
Address	Address	Address	Address
A1: A0	A1: A0	A1: A0	A1: A0
00	01	10	11

01	00	11	10

10	11	00	01

11	10	01	00