Cypress CY7C1373D Identification Register Definitions, Scan Register Sizes, Identification Codes

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CY7C1371D

CY7C1373D

Identification Register Definitions

Instruction Field

CY7C1371D

CY7C1373D

Description

(512K X 36)

(1M X 18)

 

 

 

 

Revision Number (31:29)

000

000

Describes the version number

 

 

 

 

Device Depth (28:24)

01011

01011

Reserved for internal use

 

 

 

 

Device Width (23:18)

001001

001001

Defines memory type and architecture

 

 

 

 

Cypress Device ID (17:12)

100101

010101

Defines width and density

 

 

 

 

Cypress JEDEC ID Code (11:1)

00000110100

00000110100

Allows unique identification of SRAM vendor

 

 

 

 

ID Register Presence Indicator (0)

1

1

Indicates the presence of an ID register

 

 

 

 

Scan Register Sizes

Register Name

Bit Size (x36)

Bit Size (x18)

 

 

 

Instruction

3

3

 

 

 

Bypass

1

1

 

 

 

ID

32

32

 

 

 

Boundary Scan Order (119-Ball BGA package)

85

85

 

 

 

Boundary Scan Order (165-Ball FBGA package)

89

89

 

 

 

Identification Codes

Instruction

Code

Description

 

 

 

EXTEST

000

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

 

 

Forces all SRAM outputs to High-Z state.

 

 

 

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and

 

 

TDO. This operation does not affect SRAM operations.

 

 

 

SAMPLE Z

010

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

 

 

Forces all SRAM output drivers to a High-Z state.

 

 

 

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOAD

100

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

 

 

Does not affect SRAM operation.

 

 

 

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

operations.

 

 

 

Document #: 38-05556 Rev. *F

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Contents Features Selection Guide Functional Description1133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1371D 512K x Logic Block Diagram CY7C1373D 1M xPin Configurations Pin Tqfp Pinout CY7C1371DCY7C1373D Pin Configurations Pin Configurations Ball Fbga Pinout CE2Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Partial Truth Table for Read/Write 2, 3 Address Operation UsedFunction CY7C1371D Function CY7C1373DTAP Controller State Diagram TAP Controller Block Diagram Ieee 1149.1 Serial Boundary Scan JtagBypass Register TAP Instruction SetTAP Timing Extest Output Bus Tri-StateTAP AC Switching Characteristics Over the Operating Range10 Setup TimesParameter Description Min Max Unit Clock Output Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating ConditionsParameter Description Conditions Min Max Unit Identification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBall BGA Boundary Scan Order 13 Bit # Ball IDA10 B10 P10 Electrical Characteristics Maximum RatingsOperating Range Ambient RangeThermal Resistance18 Capacitance18AC Test Loads and Waveforms Switching Characteristics Over the Operating Range23 133 MHz 100 MHz Parameter Description Unit Min MaxSwitching Waveforms Read/Write Waveforms25, 26Rite ReadNOP, Stall and Deselect Cycles25, 26 AddressStall Stall NOPZZ Mode Timing29 DON’T CareOrdering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Issue Orig. Description of Change Date Document History
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