Cypress CY7C1373D, CY7C1371D manual Pin Configurations Ball Fbga Pinout, CE2

Page 6

CY7C1371D

CY7C1373D

Pin Configurations (continued)

165-Ball FBGA Pinout

CY7C1371D (512K x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/576M

1

C

B

3

A

CE

BW

BW

CE

CEN

ADV/LD

A

A

NC

B

NC/1G

A

CE2

D

A

CLK

A

A

NC

BW

BW

WE

OE

C

DQPC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DQPB

D

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

E

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

F

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

G

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

K

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

L

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

M

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

N

DQPD

NC

VDDQ

VSS

NC

NC

NC

VSS

VDDQ

NC

DQPA

P

NC/144M

NC/72M

A

A

TDI

A1

TDO

A

A

A

NC/288M

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

CY7C1373D (1M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/576M

1

B

NC

3

A

A

A

A

CE

BW

CE

CEN

ADV/LD

B

NC/1G

A

CE2

NC

A

CLK

A

A

NC

BW

WE

OE

C

NC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DQPA

D

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

E

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

F

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

G

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

K

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

L

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

M

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

N

DQPB

NC

VDDQ

VSS

NC

NC

NC

VSS

VDDQ

NC

NC

P

NC/144M

NC/72M

A

A

TDI

A1

TDO

A

A

A

NC/288M

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

Document #: 38-05556 Rev. *F

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Contents 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description1 Cypress Semiconductor CorporationLogic Block Diagram CY7C1371D 512K x Logic Block Diagram CY7C1373D 1M xPin Configurations Pin Tqfp Pinout CY7C1371DCY7C1373D Pin Configurations Pin Configurations Ball Fbga Pinout CE2Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1371D Partial Truth Table for Read/Write 2, 3Address Operation Used Function CY7C1373DTAP Controller State Diagram TAP Controller Block Diagram Ieee 1149.1 Serial Boundary Scan JtagBypass Register TAP Instruction SetTAP Timing Extest Output Bus Tri-StateParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range10Setup Times Output TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test ConditionsParameter Description Conditions Min Max Unit Identification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 13 Bit # Ball IDA10 B10 P10 Operating Range Electrical CharacteristicsMaximum Ratings Ambient RangeCapacitance18 Thermal Resistance18AC Test Loads and Waveforms Switching Characteristics Over the Operating Range23 133 MHz 100 MHz Parameter Description Unit Min MaxRite Switching WaveformsRead/Write Waveforms25, 26 ReadStall NOP, Stall and Deselect Cycles25, 26Address Stall NOPZZ Mode Timing29 DON’T CareOrdering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Issue Orig. Description of Change Date Document History