Cypress CY7C1371D, CY7C1373D manual Pin Definitions

CY7C1371D

CY7C1373D

Pin Definitions

Name

IO

Description

A0, A1, A

Input-

Address Inputs used to select one of the address locations. Sampled at the rising edge of the

Synchronous

CLK. A[1:0] are fed to the two-bit burst counter.

A,

Input-

Byte Write Inputs, Active LOW. Qualified with

to conduct writes to the SRAM. Sampled on

BW

BW

B

WE

BWC, BWD

Synchronous

the rising edge of CLK.

Input-

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if

is active LOW. This

WE

CEN

Synchronous

signal must be asserted LOW to initiate a write sequence.

Input-

Advance/Load Input. Used to advance the on-chip address counter or load a new address. When

ADV/LD

Synchronous

HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new

address can be loaded into the device for an access. After being deselected, ADV/LD must be

driven LOW to load a new address.

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with

CLK

CEN.

Clock

is only recognized if CEN is active LOW.

1

Input-

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE

Synchronous

CE2 and CE3 to select/deselect the device.

CE2

Input-

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous

CE1 and CE3 to select/deselect the device.

3

Input-

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE

Synchronous

CE1 and CE2 to select/deselect the device.

Input-

Output Enable, asynchronous input, Active LOW. Combined with the synchronous logic block

OE

Asynchronous

inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to

behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins.

OE

is masked during the data portion of a write sequence, during the first clock when emerging from

a deselected state, when the device has been deselected.

Input-

Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the

CEN

Synchronous

SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN does not

deselect the device, use CEN to extend the previous cycle when required.

ZZ

Input-

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

Asynchronous

with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin

has an internal pull down.

DQs

IO-

Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by

Synchronous

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

by the addresses presented during the previous clock rise of the read cycle. The direction of the

pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,

DQs and DQP[A:D] are placed in a tri-state condition.The outputs are automatically tri-stated during

the data portion of a write sequence, during the first clock when emerging from a deselected state,

and when the device is deselected, regardless of the state of OE.

DQPX

IO-

Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs.

Synchronous

MODE

Input Strap Pin

Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved

burst sequence.

VDD

Power Supply

Power supply inputs to the core of the device.

VDDQ

IO Power

Power supply for the IO circuitry.

Supply

VSS

Ground

Ground for the device.

Document #: 38-05556 Rev. *F Page 7 of 29

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