Cypress CY7C1371D, CY7C1373D manual Pin Configurations

Page 5

CY7C1371D

CY7C1373D

Pin Configurations (continued)

119-Ball BGA Pinout CY7C1371D (512K x 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

A

VDDQ

B

NC/576M

CE2

A

A

ADV/LD

CE

3

NC

C

NC/1G

A

A

VDD

A

A

NC

D

DQC

DQPC

VSS

NC

VSS

DQPB

DQB

E

DQC

DQC

VSS

1

VSS

DQB

DQB

CE

F

VDDQ

DQC

VSS

VSS

DQB

VDDQ

OE

G

DQC

DQC

C

A

B

DQB

DQB

BW

BW

H

DQC

DQC

VSS

VSS

DQB

DQB

WE

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD

DQD

VSS

CLK

VSS

DQA

DQA

L

DQD

DQD

D

NC

A

DQA

DQA

BW

BW

M

VDDQ

DQD

VSS

VSS

DQA

VDDQ

CEN

N

DQD

DQD

VSS

A1

VSS

DQA

DQA

P

DQD

DQPD

VSS

A0

VSS

DQPA

DQA

R

NC/144M

A

MODE

VDD

NC

A

NC/288M

T

NC

NC/72M

A

A

A

NC/36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1373D (1Mx 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

A

VDDQ

B

NC/576M

CE2

A

A

NC

ADV/LD

CE

3

C

NC/1G

A

A

VDD

A

A

NC

D

DQB

NC

VSS

NC

VSS

DQPA

NC

E

NC

DQB

VSS

1

VSS

NC

DQA

CE

F

VDDQ

NC

VSS

VSS

DQA

VDDQ

OE

G

NC

DQB

B

A

NC

NC

DQA

BW

H

DQB

NC

VSS

VSS

DQA

NC

WE

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB

VSS

CLK

VSS

NC

DQA

L

DQB

NC

NC

NC

A

DQA

NC

BW

M

VDDQ

DQB

VSS

VSS

NC

VDDQ

CEN

N

DQB

NC

VSS

A1

VSS

DQA

NC

P

NC

DQPB

VSS

A0

VSS

NC

DQA

R

NC/144M

A

MODE

VDD

NC

A

NC/288M

T

NC/72M

A

A

NC/36M

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document #: 38-05556 Rev. *F

Page 5 of 29

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Contents Selection Guide Functional Description1 Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1373D 1M x Logic Block Diagram CY7C1371D 512K xCY7C1371D Pin Configurations Pin Tqfp PinoutCY7C1373D Pin Configurations CE2 Pin Configurations Ball Fbga PinoutPin Definitions Burst Read Accesses Single Read AccessesSingle Write Accesses Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Address Operation Used Partial Truth Table for Read/Write 2, 3Function CY7C1371D Function CY7C1373DIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State Diagram TAP Controller Block DiagramTAP Instruction Set Bypass RegisterExtest Output Bus Tri-State TAP TimingSetup Times TAP AC Switching Characteristics Over the Operating Range10Parameter Description Min Max Unit Clock Output TimesParameter Description Conditions Min Max Unit TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Scan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 13A10 B10 P10 Maximum Ratings Electrical CharacteristicsOperating Range Ambient RangeAC Test Loads and Waveforms Capacitance18Thermal Resistance18 133 MHz 100 MHz Parameter Description Unit Min Max Switching Characteristics Over the Operating Range23Read/Write Waveforms25, 26 Switching WaveformsRite ReadAddress NOP, Stall and Deselect Cycles25, 26Stall Stall NOPDON’T Care ZZ Mode Timing29Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History Issue Orig. Description of Change Date