Cypress CY7C1371D, CY7C1373D manual TAP Timing, Extest Output Bus Tri-State

Page 13

CY7C1371D

CY7C1373D

boundary scan path when multiple devices are connected together on a board.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #85 (for 119-BGA package) or bit #89 (for 165-fBGA package). When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1

2

Test Clock

 

(TCK)

tTH

 

tTMSS

tTMSH

Test Mode Select

 

(TMS)

 

tTDIS

tTDIH

Test Data-In

 

(TDI)

 

3

4

5

6

tTL tCYC

tTDOV

tTDOX

Test Data-Out (TDO)

DON’T CARE

UNDEFINED

Document #: 38-05556 Rev. *F

Page 13 of 29

[+] Feedback

Page 12 Page 14
Image 13
Page 12 Page 14
Contents Selection Guide Functional Description1 Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1373D 1M x Logic Block Diagram CY7C1371D 512K xCY7C1371D Pin Configurations Pin Tqfp PinoutCY7C1373D Pin Configurations CE2 Pin Configurations Ball Fbga PinoutPin Definitions Burst Read Accesses Single Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Operation Used Partial Truth Table for Read/Write 2, 3Function CY7C1371D Function CY7C1373DIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State Diagram TAP Controller Block DiagramTAP Instruction Set Bypass RegisterExtest Output Bus Tri-State TAP TimingSetup Times TAP AC Switching Characteristics Over the Operating Range10Parameter Description Min Max Unit Clock Output Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating ConditionsParameter Description Conditions Min Max Unit Scan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 13A10 B10 P10 Maximum Ratings Electrical CharacteristicsOperating Range Ambient RangeThermal Resistance18 Capacitance18AC Test Loads and Waveforms 133 MHz 100 MHz Parameter Description Unit Min Max Switching Characteristics Over the Operating Range23Read/Write Waveforms25, 26 Switching WaveformsRite ReadAddress NOP, Stall and Deselect Cycles25, 26Stall Stall NOPDON’T Care ZZ Mode Timing29Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History Issue Orig. Description of Change Date
Top Page Image Contents