Cypress manual Logic Block Diagram CY7C1371D 512K x, Logic Block Diagram CY7C1373D 1M x

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CY7C1371D

CY7C1373D

Logic Block Diagram – CY7C1371D (512K x 36)

	A0, A1, A	ADDRESS	A1			A1'
	A0, A1, A	REGISTER
		REGISTER		D1	Q1
	MODE		A0	D0	Q0	A0'
		CE	ADV/LD		BURST
CLK	C	CE			LOGIC
CLK	C				LOGIC
CEN			C
			WRITE ADDRESS
			REGISTER							O
										O
										U
										T
								S	D	P
								S	A	U
								E	T	T
	ADV/LD							N	A
	BW A						MEMORY	S		B
	BW A		WRITE REGISTRY			WRITE	ARRAY	E	S	U
			WRITE REGISTRY			WRITE	ARRAY	E	S	U
	BW B		AND DATA COHERENCY			DRIVERS		A	T	F
	BW C		CONTROL LOGIC					A	E	F
	BW C							M	E	E
	BW D							P	R	R
	BW D							S	I	S
	WE							S	I	S
	WE								N	E
									G
							INPUT	E
							REGISTER	E
	OE						REGISTER
	OE	READ LOGIC
	CE1	READ LOGIC
	CE1
	CE2
	CE3		SLEEP
	ZZ		SLEEP
	ZZ	CONTROL
		CONTROL

DQs

DQP A DQP B DQP C DQP D

Logic Block Diagram – CY7C1373D (1M x 18)

A0, A1, A

ADDRESS

A1

A1'

REGISTER

D1

Q1

MODE

A0

D0

Q0

A0'

CE

ADV/LD

BURST

CLK

C

LOGIC

CEN

C

WRITE ADDRESS

REGISTER

O

U

T

S

D

P

A

U

E

T

T

ADV/LD

N

A

BW A

MEMORY

S

B

WRITE REGISTRY

WRITE

ARRAY

E

S

U

DQs

BW B

AND DATA COHERENCY

DRIVERS

A

T

F

DQP A

CONTROL LOGIC

E

F

DQP B

M

E

E

P

R

R

WE

S

I

S

E

N

G

INPUT

E

REGISTER

OE

READ LOGIC

CE1

CE2

CE3

ZZ

SLEEP

CONTROL

Document #: 38-05556 Rev. *F

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Contents 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description1 Cypress Semiconductor CorporationLogic Block Diagram CY7C1371D 512K x Logic Block Diagram CY7C1373D 1M xPin Configurations Pin Tqfp Pinout CY7C1371DCY7C1373D Pin Configurations Pin Configurations Ball Fbga Pinout CE2Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1371D Partial Truth Table for Read/Write 2, 3Address Operation Used Function CY7C1373DTAP Controller State Diagram TAP Controller Block Diagram Ieee 1149.1 Serial Boundary Scan JtagBypass Register TAP Instruction SetTAP Timing Extest Output Bus Tri-StateParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range10Setup Times Output TimesParameter Description Conditions Min Max Unit TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Identification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 13 Bit # Ball IDA10 B10 P10 Operating Range Electrical CharacteristicsMaximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance18Thermal Resistance18 Switching Characteristics Over the Operating Range23 133 MHz 100 MHz Parameter Description Unit Min MaxRite Switching WaveformsRead/Write Waveforms25, 26 ReadStall NOP, Stall and Deselect Cycles25, 26Address Stall NOPZZ Mode Timing29 DON’T CareOrdering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Issue Orig. Description of Change Date Document History