Cypress CY7C1373D, CY7C1371D manual A10 B10 P10

Page 18

CY7C1371D

CY7C1373D

165-Ball BGA Boundary Scan Order [13, 15]

Bit #

Ball ID

 

Bit #

Ball ID

 

Bit #

Ball ID

 

 

 

 

 

 

 

 

1

N6

 

31

D10

 

61

G1

 

 

 

 

 

 

 

 

2

N7

 

32

C11

 

62

D2

 

 

 

 

 

 

 

 

3

N10

 

33

A11

 

63

E2

 

 

 

 

 

 

 

 

4

P11

 

34

B11

 

64

F2

 

 

 

 

 

 

 

 

5

P8

 

35

A10

 

65

G2

 

 

 

 

 

 

 

 

6

R8

 

36

B10

 

66

H1

 

 

 

 

 

 

 

 

7

R9

 

37

A9

 

67

H3

 

 

 

 

 

 

 

 

8

P9

 

38

B9

 

68

J1

 

 

 

 

 

 

 

 

9

P10

 

39

C10

 

69

K1

 

 

 

 

 

 

 

 

10

R10

 

40

A8

 

70

L1

 

 

 

 

 

 

 

 

11

R11

 

41

B8

 

71

M1

 

 

 

 

 

 

 

 

12

H11

 

42

A7

 

72

J2

 

 

 

 

 

 

 

 

13

N11

 

43

B7

 

73

K2

 

 

 

 

 

 

 

 

14

M11

 

44

B6

 

74

L2

 

 

 

 

 

 

 

 

15

L11

 

45

A6

 

75

M2

 

 

 

 

 

 

 

 

16

K11

 

46

B5

 

76

N1

 

 

 

 

 

 

 

 

17

J11

 

47

A5

 

77

N2

 

 

 

 

 

 

 

 

18

M10

 

48

A4

 

78

P1

 

 

 

 

 

 

 

 

19

L10

 

49

B4

 

79

R1

 

 

 

 

 

 

 

 

20

K10

 

50

B3

 

80

R2

 

 

 

 

 

 

 

 

21

J10

 

51

A3

 

81

P3

 

 

 

 

 

 

 

 

22

H9

 

52

A2

 

82

R3

 

 

 

 

 

 

 

 

23

H10

 

53

B2

 

83

P2

 

 

 

 

 

 

 

 

24

G11

 

54

C2

 

84

R4

 

 

 

 

 

 

 

 

25

F11

 

55

B1

 

85

P4

 

 

 

 

 

 

 

 

26

E11

 

56

A1

 

86

N5

 

 

 

 

 

 

 

 

27

D11

 

57

C1

 

87

P6

 

 

 

 

 

 

 

 

28

G10

 

58

D1

 

88

R6

 

 

 

 

 

 

 

 

29

F10

 

59

E1

 

89

Internal

 

 

 

 

 

 

 

 

30

E10

 

60

F1

 

 

 

 

 

 

 

 

 

 

 

Note:

15. Bit# 89 is pre-set HIGH.

Document #: 38-05556 Rev. *F

Page 18 of 29

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Image 18
Contents 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description1 Cypress Semiconductor CorporationLogic Block Diagram CY7C1371D 512K x Logic Block Diagram CY7C1373D 1M xPin Configurations Pin Tqfp Pinout CY7C1371DCY7C1373D Pin Configurations Pin Configurations Ball Fbga Pinout CE2Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1371D Partial Truth Table for Read/Write 2, 3Address Operation Used Function CY7C1373DTAP Controller State Diagram TAP Controller Block Diagram Ieee 1149.1 Serial Boundary Scan JtagBypass Register TAP Instruction SetTAP Timing Extest Output Bus Tri-StateParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range10Setup Times Output TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test ConditionsParameter Description Conditions Min Max Unit Identification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 13 Bit # Ball IDA10 B10 P10 Operating Range Electrical CharacteristicsMaximum Ratings Ambient RangeCapacitance18 Thermal Resistance18AC Test Loads and Waveforms Switching Characteristics Over the Operating Range23 133 MHz 100 MHz Parameter Description Unit Min MaxRite Switching WaveformsRead/Write Waveforms25, 26 ReadStall NOP, Stall and Deselect Cycles25, 26Address Stall NOPZZ Mode Timing29 DON’T CareOrdering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Issue Orig. Description of Change Date Document History