Cypress CY7C1373D, CY7C1371D manual Ball Fbga 13 x 15 x 1.4 mm

Page 28

CY7C1371D

CY7C1373D

Package Diagrams (continued)

Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

15.00±0.10

TOP VIEW

PIN 1 CORNER

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

15.00±0.10

14.00

BOTTOM VIEW

PIN 1 CORNER

Ø0.05 M C Ø0.25 M C A B

-0.06

Ø0.50 (165X)

+0.14

11

10

9

8

7

6

5

4

3

2

1

1.00

7.00

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

A

B

0.25 C

0.53±0.05

 

0.36

13.00±0.10

SEATING PLANE

C

1.40MAX.

 

0.15C

 

 

 

 

 

 

0.35±0.06

A

1.00

5.00

10.00

B

13.00±0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC

51-85180-*A

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05556 Rev. *F

Page 28 of 29

© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Contents Features Selection Guide Functional Description1133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1371D 512K x Logic Block Diagram CY7C1373D 1M xPin Configurations Pin Tqfp Pinout CY7C1371DCY7C1373D Pin Configurations Pin Configurations Ball Fbga Pinout CE2Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Partial Truth Table for Read/Write 2, 3 Address Operation UsedFunction CY7C1371D Function CY7C1373DTAP Controller State Diagram TAP Controller Block Diagram Ieee 1149.1 Serial Boundary Scan JtagBypass Register TAP Instruction SetTAP Timing Extest Output Bus Tri-StateTAP AC Switching Characteristics Over the Operating Range10 Setup TimesParameter Description Min Max Unit Clock Output Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating ConditionsParameter Description Conditions Min Max Unit Identification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBall BGA Boundary Scan Order 13 Bit # Ball IDA10 B10 P10 Electrical Characteristics Maximum RatingsOperating Range Ambient RangeThermal Resistance18 Capacitance18AC Test Loads and Waveforms Switching Characteristics Over the Operating Range23 133 MHz 100 MHz Parameter Description Unit Min MaxSwitching Waveforms Read/Write Waveforms25, 26Rite ReadNOP, Stall and Deselect Cycles25, 26 AddressStall Stall NOPZZ Mode Timing29 DON’T CareOrdering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Issue Orig. Description of Change Date Document History
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