Cypress CY7C1372DV25 manual Identification Codes, Ball BGA Boundary Scan Order 12, Bit # Ball ID

Page 15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1370DV25

 

Identification Codes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1372DV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

Code

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXTEST

 

 

000

 

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

 

 

 

 

 

 

 

Forces all SRAM outputs to High-Z state.

 

 

 

 

 

IDCODE

 

 

001

 

Loads the ID register with the vendor ID code and places the register between TDI and

 

 

 

 

 

 

 

 

 

 

 

TDO. This operation does not affect SRAM operations.

 

 

 

 

 

SAMPLE Z

 

 

010

 

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

 

 

 

 

 

 

 

Forces all SRAM output drivers to a High-Z state.

 

 

 

 

 

RESERVED

 

 

011

 

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SAMPLE/PRELOAD

 

100

 

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

 

 

 

 

 

 

 

Does not affect SRAM operation.

 

 

 

 

 

 

 

RESERVED

 

 

101

 

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESERVED

 

 

110

 

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BYPASS

 

 

111

 

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

 

 

 

 

 

 

 

 

 

operations.

 

 

 

 

 

 

 

 

 

119-Ball BGA Boundary Scan Order [12, 13]

 

 

 

 

 

 

 

 

 

Bit #

 

Ball ID

 

 

 

 

 

Bit #

 

Ball ID

 

Bit #

 

Ball ID

 

Bit #

Ball ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

H4

 

 

 

 

 

23

 

F6

 

45

 

G4

 

67

L1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

T4

 

 

 

 

 

24

 

E7

 

46

 

A4

 

68

M2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

T5

 

 

 

 

 

25

 

D7

 

47

 

G3

 

69

N1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

T6

 

 

 

 

 

26

 

H7

 

48

 

C3

 

70

P1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

R5

 

 

 

 

 

27

 

G6

 

49

 

B2

 

71

K1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

L5

 

 

 

 

 

28

 

E6

 

50

 

B3

 

72

L2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

R6

 

 

 

 

 

29

 

D6

 

51

 

A3

 

73

N2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

U6

 

 

 

 

 

30

 

C7

 

52

 

C2

 

74

P2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

R7

 

 

 

 

 

31

 

B7

 

53

 

A2

 

75

R3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

T7

 

 

 

 

 

32

 

C6

 

54

 

B1

 

76

T1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

P6

 

 

 

 

 

33

 

A6

 

55

 

C1

 

77

R1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

N7

 

 

 

 

 

34

 

C5

 

56

 

D2

 

78

T2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

M6

 

 

 

 

 

35

 

B5

 

57

 

E1

 

79

L3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

L7

 

 

 

 

 

36

 

G5

 

58

 

F2

 

80

R2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

K6

 

 

 

 

 

37

 

B6

 

59

 

G1

 

81

T3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

P7

 

 

 

 

 

38

 

D4

 

60

 

H2

 

82

L4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

 

N6

 

 

 

 

 

39

 

B4

 

61

 

D1

 

83

N4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

 

L6

 

 

 

 

 

40

 

F4

 

62

 

E2

 

84

P4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

K7

 

 

 

 

 

41

 

M4

 

63

 

G2

 

85

Internal

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

J5

 

 

 

 

 

42

 

A5

 

64

 

H1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

 

H6

 

 

 

 

 

43

 

K4

 

65

 

J3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22

 

G7

 

 

 

 

 

44

 

E4

 

66

 

2K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

12.Balls which are NC (No Connect) are pre-set LOW.

13.Bit# 85 is pre-set HIGH.

Document #: 38-05558 Rev. *D

Page 15 of 27

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1370DV25 512K x Functional DescriptionLogic Block Diagram-CY7C1372DV25 1M x Selection Guide250 MHz 200 MHz 167 MHz Unit 1M × Pin Configurations Pin Tqfp PinoutCY7C1370DV25 512K × Pin Configurations Ball BGA PinoutPin Configurations Ball Fbga Pinout Clock input to the Jtag circuitry Pin DefinitionsPin Name Type Pin Description Byte Write Select Inputs, active LOW. Qualified withIntroduction Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Partial Write Cycle Description 1, 2, 3 Address Operation UsedFunction CY7C1370DV25 TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set TAP RegistersBypass TAP TimingHold Times TAP AC Switching Characteristics Over the Operating Range9Parameter Description Min Max Unit Clock Output TimesScan Register Sizes TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentBit # Ball ID Identification CodesBall BGA Boundary Scan Order 12 Instruction Code DescriptionBall Fbga Boundary Scan Order 12 Range Ambient Electrical Characteristics Over the Operating Range15Maximum Ratings Operating RangePackage Capacitance17Thermal Resistance17 AC Test Loads and WaveformsSwitching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSet-up Times DON’T Care Switching WaveformsRead/Write/Timing24, 25 Address A1 A2NOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information CY7C1370DV25 CY7C1372DV25 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History ECN No Issue Date Orig. Description of Change