Cypress manual CY7C1370DV25 CY7C1372DV25

Page 23

CY7C1370DV25

CY7C1372DV25

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

250	CY7C1370DV25-250AXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free	Commercial
	CY7C1372DV25-250AXC

	CY7C1370DV25-250BGC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1372DV25-250BGC

	CY7C1370DV25-250BGXC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

	CY7C1372DV25-250BGXC

	CY7C1370DV25-250BZC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1372DV25-250BZC

	CY7C1370DV25-250BZXC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
			Lead-Free
	CY7C1372DV25-250BZXC		Lead-Free
	CY7C1372DV25-250BZXC

	CY7C1370DV25-250AXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free	Industrial

	CY7C1372DV25-250AXI

	CY7C1370DV25-250BGI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1372DV25-250BGI

	CY7C1370DV25-250BGXI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

	CY7C1372DV25-250BGXI

	CY7C1370DV25-250BZI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1372DV25-250BZI

	CY7C1370DV25-250BZXI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
			Lead-Free
	CY7C1372DV25-250BZXI		Lead-Free
	CY7C1372DV25-250BZXI

Document #: 38-05558 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1370DV25 512K x Functional Description250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1372DV25 1M xSelection Guide 1M × Pin Configurations Pin Tqfp PinoutCY7C1370DV25 512K × Pin Configurations Ball BGA PinoutPin Configurations Ball Fbga Pinout Clock input to the Jtag circuitry Pin DefinitionsPin Name Type Pin Description Byte Write Select Inputs, active LOW. Qualified withIntroduction ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1370DV25 Partial Write Cycle Description 1, 2, 3Address Operation Used Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set TAP RegistersBypass TAP TimingHold Times TAP AC Switching Characteristics Over the Operating Range9Parameter Description Min Max Unit Clock Output TimesScan Register Sizes TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentBit # Ball ID Identification CodesBall BGA Boundary Scan Order 12 Instruction Code DescriptionBall Fbga Boundary Scan Order 12 Range Ambient Electrical Characteristics Over the Operating Range15Maximum Ratings Operating RangePackage Capacitance17Thermal Resistance17 AC Test Loads and WaveformsSet-up Times Switching Characteristics Over the Operating Range 22250 200 167 Parameter Description Unit Min Max DON’T Care Switching WaveformsRead/Write/Timing24, 25 Address A1 A2NOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information CY7C1370DV25 CY7C1372DV25 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History ECN No Issue Date Orig. Description of Change