Cypress CY7C1370DV25 Switching Waveforms, Read/Write/Timing24, 25, Address A1 A2, DON’T Care

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CY7C1370DV25

CY7C1372DV25

Switching Waveforms

Read/Write/Timing[24, 25, 26]

1

2 t CYC 3

CLK

 

tCENS tCENH

tCH tCL

CEN

tCES tCEH

CE

ADV/LD

WE

BWx

ADDRESS A1 A2

 

4

 

5

6

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3

A4

A5

 

tCO

 

8 9

A6 A7

10

tAS tAH

tDS tDH

tCLZ

tDOH

tOEV tCHZ

Data

D(A1)

In-Out (DQ)

OE

D(A2) D(A2+1) Q(A3) Q(A4)

tOEHZ

Q(A4+1) D(A5)

tDOH tOELZ

Q(A6)

WRITE

WRITE

BURST

D(A1)

D(A2)

WRITE

 

 

D(A2+1)

READ

READ

BURST

WRITE

READ

WRITE

Q(A3)

Q(A4)

READ

D(A5)

Q(A6)

D(A7)

 

 

Q(A4+1)

 

 

 

DESELECT

DON’T CARE

UNDEFINED

Notes:

24.For this waveform ZZ is tied LOW.

25.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

26.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

Document #: 38-05558 Rev. *D

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Contents Features Logic Block Diagram-CY7C1370DV25 512K xFunctional Description Cypress Semiconductor Corporation250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1372DV25 1M xSelection Guide Pin Configurations Pin Tqfp Pinout 1M ×Pin Configurations Ball BGA Pinout CY7C1370DV25 512K ×Pin Configurations Ball Fbga Pinout Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with Clock input to the Jtag circuitryIntroduction ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1370DV25 Partial Write Cycle Description 1, 2, 3Address Operation Used Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Registers TAP Instruction SetTAP Timing BypassTAP AC Switching Characteristics Over the Operating Range9 Parameter Description Min Max Unit ClockOutput Times Hold TimesTAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order 12Instruction Code Description Bit # Ball IDBall Fbga Boundary Scan Order 12 Electrical Characteristics Over the Operating Range15 Maximum RatingsOperating Range Range AmbientCapacitance17 Thermal Resistance17AC Test Loads and Waveforms PackageSet-up Times Switching Characteristics Over the Operating Range 22250 200 167 Parameter Description Unit Min Max Switching Waveforms Read/Write/Timing24, 25Address A1 A2 DON’T CareZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information CY7C1370DV25 CY7C1372DV25 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document History