Cypress CY7C1372DV25, CY7C1370DV25 manual Pin Configurations Ball Fbga Pinout

Page 5

CY7C1370DV25

CY7C1372DV25

Pin Configurations (continued)

165-Ball FBGA Pinout

CY7C1370DV25 (512K × 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/576M

A

A

A

NC

CE

1

BW

c

BW

b

CE

3

CEN

ADV/LD

B

NC/1G

A

CE2

d

a

CLK

A

A

NC

BW

BW

WE

OE

C

DQPc

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DQPb

D

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

E

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

F

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

G

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

K

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

L

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

M

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

N

DQPd

NC

VDDQ

VSS

NC

NC

NC

VSS

VDDQ

NC

DQPa

P

NC/144M

NC/72M

A

A

TDI

A1

TDO

A

A

A

NC/288M

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

CY7C1372DV25 (1M × 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/576M

A

NC

A

A

A

CE

1

BW

b

CE

3

CEN

ADV/LD

B

NC/1G

A

CE2

NC

CLK

A

A

NC

BW

a

WE

OE

C

NC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DQPa

D

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

E

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

F

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

G

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

K

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

L

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

M

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

N

DQPb

NC

VDDQ

VSS

NC

NC

NC

VSS

VDDQ

NC

NC

P

NC/144M

NC/72M

A

A

TDI

A1

TDO

A

A

A

NC/288M

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

Document #: 38-05558 Rev. *D

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Contents Logic Block Diagram-CY7C1370DV25 512K x FeaturesFunctional Description Cypress Semiconductor Corporation250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1372DV25 1M xSelection Guide 1M × Pin Configurations Pin Tqfp PinoutCY7C1370DV25 512K × Pin Configurations Ball BGA PinoutPin Configurations Ball Fbga Pinout Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Clock input to the Jtag circuitryIntroduction ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1370DV25 Partial Write Cycle Description 1, 2, 3Address Operation Used Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set TAP RegistersBypass TAP TimingParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range9Output Times Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Output Load Equivalent Scan Register SizesBall BGA Boundary Scan Order 12 Identification CodesInstruction Code Description Bit # Ball IDBall Fbga Boundary Scan Order 12 Maximum Ratings Electrical Characteristics Over the Operating Range15Operating Range Range AmbientThermal Resistance17 Capacitance17AC Test Loads and Waveforms PackageSet-up Times Switching Characteristics Over the Operating Range 22250 200 167 Parameter Description Unit Min Max Read/Write/Timing24, 25 Switching WaveformsAddress A1 A2 DON’T CareNOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information CY7C1370DV25 CY7C1372DV25 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History ECN No Issue Date Orig. Description of Change