Cypress CY7C1370DV25, CY7C1372DV25 manual Ordering Information

Page 22

CY7C1370DV25

CY7C1372DV25

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

Ordering Code

Package

Part and Package Type

Operating

(MHz)

Diagram

Range

 

 

 

 

 

167

CY7C1370DV25-167AXC

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

 

 

 

 

 

 

CY7C1372DV25-167AXC

 

 

 

 

 

 

 

 

 

CY7C1370DV25-167BGC

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm)

 

 

 

 

 

 

 

CY7C1372DV25-167BGC

 

 

 

 

 

 

 

 

 

CY7C1370DV25-167BGXC

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

 

 

 

 

 

 

 

CY7C1372DV25-167BGXC

 

 

 

 

 

 

 

 

 

CY7C1370DV25-167BZC

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

 

 

 

CY7C1372DV25-167BZC

 

 

 

 

 

 

 

 

 

CY7C1370DV25-167BZXC

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

Lead-Free

 

 

CY7C1372DV25-167BZXC

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1370DV25-167AXI

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

 

 

 

 

 

 

CY7C1372DV25-167AXI

 

 

 

 

 

 

 

 

 

CY7C1370DV25-167BGI

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm)

 

 

 

 

 

 

 

CY7C1372DV25-167BGI

 

 

 

 

 

 

 

 

 

CY7C1370DV25-167BGXI

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

 

 

 

 

 

 

 

CY7C1372DV25-167BGXI

 

 

 

 

 

 

 

 

 

CY7C1370DV25-167BZI

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

 

 

 

CY7C1372DV25-167BZI

 

 

 

 

 

 

 

 

 

CY7C1370DV25-167BZXI

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

Lead-Free

 

 

CY7C1372DV25-167BZXI

 

 

 

 

 

 

 

 

 

 

 

200

CY7C1370DV25-200AXC

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

 

 

 

 

 

 

CY7C1372DV25-200AXC

 

 

 

 

 

 

 

 

 

CY7C1370DV25-200BGC

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm)

 

 

 

 

 

 

 

CY7C1372DV25-200BGC

 

 

 

 

 

 

 

 

 

CY7C1370DV25-200BGXC

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

 

 

 

 

 

 

 

CY7C1372DV25-200BGXC

 

 

 

 

 

 

 

 

 

CY7C1370DV25-200BZC

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

 

 

 

CY7C1372DV25-200BZC

 

 

 

 

 

 

 

 

 

CY7C1370DV25-200BZXC

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

Lead-Free

 

 

CY7C1372DV25-200BZXC

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1370DV25-200AXI

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

 

 

 

 

 

 

CY7C1372DV25-200AXI

 

 

 

 

 

 

 

 

 

CY7C1370DV25-200BGI

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm)

 

 

 

 

 

 

 

CY7C1372DV25-200BGI

 

 

 

 

 

 

 

 

 

CY7C1370DV25-200BGXI

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

 

 

 

 

 

 

 

CY7C1372DV25-200BGXI

 

 

 

 

 

 

 

 

 

CY7C1370DV25-200BZI

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

 

 

 

CY7C1372DV25-200BZI

 

 

 

 

 

 

 

 

 

CY7C1370DV25-200BZXI

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

Lead-Free

 

 

CY7C1372DV25-200BZXI

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-05558 Rev. *D

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1370DV25 512K x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1372DV25 1M x250 MHz 200 MHz 167 MHz Unit Pin Configurations Pin Tqfp Pinout 1M ×Pin Configurations Ball BGA Pinout CY7C1370DV25 512K ×Pin Configurations Ball Fbga Pinout Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsPin Name Type Pin Description Clock input to the Jtag circuitryIntroduction Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Operation Used Partial Write Cycle Description 1, 2, 3Function CY7C1370DV25 TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassOutput Times TAP AC Switching Characteristics Over the Operating Range9Parameter Description Min Max Unit Clock Hold Times5V TAP AC Output Load Equivalent TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Scan Register SizesInstruction Code Description Identification CodesBall BGA Boundary Scan Order 12 Bit # Ball IDBall Fbga Boundary Scan Order 12 Operating Range Electrical Characteristics Over the Operating Range15Maximum Ratings Range AmbientAC Test Loads and Waveforms Capacitance17Thermal Resistance17 Package250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 22Set-up Times Address A1 A2 Switching WaveformsRead/Write/Timing24, 25 DON’T CareZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information CY7C1370DV25 CY7C1372DV25 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document History