Cypress CY7C1372DV25 manual Features, Functional Description, Cypress Semiconductor Corporation

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CY7C1370DV25

CY7C1372DV25

18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture

Features

Pin-compatible and functionally equivalent to ZBT™

Supports 250-MHz bus operations with zero wait states

Available speed grades are 250, 200 and 167 MHz

Internally self-timed output buffer control to eliminate the need to use asynchronous OE

Fully registered (inputs and outputs) for pipelined operation

Byte Write capability

Single 2.5V core power supply (VDD)

2.5V I/O power supply (VDDQ)

Fast clock-to-output times

2.6 ns (for 250-MHz device)

Clock Enable (CEN) pin to suspend operation

Synchronous self-timed writes

Available in JEDEC-standard lead-free 100-Pin TQFP, lead-free and non-lead-free 119-Ball BGA and 165-Ball FBGA packages

IEEE 1149.1 JTAG-Compatible Boundary Scan

Burst capability—linear or interleaved burst order

“ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x 36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370DV25 and CY7C1372DV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370DV25 and CY7C1372DV25 are pin-compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects (BWa–BWdfor CY7C1370DV25 and BWa–BWbfor CY7C1372DV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

Logic Block Diagram-CY7C1370DV25 (512K x 36)

 

 

 

 

 

 

 

 

 

A0, A1, A

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REGISTER 0

 

A1

D1

Q1 A1'

 

 

 

 

 

 

 

 

 

MODE

 

 

A0

D0 BURST Q0 A0'

 

 

 

 

 

 

 

 

 

 

 

ADV/LD

 

LOGIC

 

 

 

 

 

 

 

 

CLK

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

CEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE ADDRESS

 

WRITE ADDRESS

 

 

 

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

O

 

O

 

 

 

 

 

 

 

 

 

 

 

U

D

 

 

 

 

 

 

 

 

 

 

 

E

T

U

 

 

 

 

 

 

 

 

 

 

 

P

A

T

 

 

 

 

 

 

 

 

 

 

 

N

 

 

 

 

 

 

 

 

 

 

 

U

T

P

 

 

 

ADV/LD

 

 

 

 

 

 

 

S

T

A

U

 

 

 

 

 

 

 

 

 

 

R

T

 

 

 

 

 

WRITE REGISTRY

 

 

MEMORY

E

S

B

 

 

 

BWa

 

AND DATA COHERENCY

 

WRITE

 

E

DQs

 

 

 

 

 

ARRAY

 

 

 

BWb

 

CONTROL LOGIC

 

DRIVERS

 

A

G

T

U

DQPa

 

 

 

 

 

 

 

 

I

F

 

 

BWc

 

 

 

 

 

 

 

M

S

E

DQPb

 

 

 

 

 

 

 

 

 

F

 

 

BWd

 

 

 

 

 

 

 

P

T

E

E

DQPc

 

 

 

 

 

 

 

 

 

 

E

 

 

WE

 

 

 

 

 

 

 

S

R

R

R

DQPd

 

 

 

 

 

 

 

 

 

 

 

S

I

S

 

 

 

 

 

 

 

 

 

 

 

 

E

N

E

 

 

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

 

 

INPUT

E

 

INPUT

E

 

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 0

 

 

 

OE

READ LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

CE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZZ

SLEEP

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document #: 38-05558 Rev. *D

 

 

 

 

 

 

 

 

 

 

Revised June 29, 2006

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Contents Logic Block Diagram-CY7C1370DV25 512K x FeaturesFunctional Description Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1372DV25 1M x250 MHz 200 MHz 167 MHz Unit 1M × Pin Configurations Pin Tqfp PinoutCY7C1370DV25 512K × Pin Configurations Ball BGA PinoutPin Configurations Ball Fbga Pinout Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Clock input to the Jtag circuitryIntroduction Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Operation Used Partial Write Cycle Description 1, 2, 3Function CY7C1370DV25 TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set TAP RegistersBypass TAP TimingParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range9Output Times Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Output Load Equivalent Scan Register SizesBall BGA Boundary Scan Order 12 Identification CodesInstruction Code Description Bit # Ball IDBall Fbga Boundary Scan Order 12 Maximum Ratings Electrical Characteristics Over the Operating Range15Operating Range Range AmbientThermal Resistance17 Capacitance17AC Test Loads and Waveforms Package250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 22Set-up Times Read/Write/Timing24, 25 Switching WaveformsAddress A1 A2 DON’T CareNOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information CY7C1370DV25 CY7C1372DV25 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History ECN No Issue Date Orig. Description of Change