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| CY7C1370DV25 | |||||
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| CY7C1372DV25 | |||||
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| Pin Definitions |
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| Pin Name | I/O Type | Pin Description | ||||||||||||||||||
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| A0 | Input- | Address Inputs used to select one of the address locations. Sampled at the rising edge of | ||||||||||||||||||
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| A1 | Synchronous | the CLK. | ||||||||||||||||||
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| A |
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| a | Input- | Byte Write Select Inputs, active LOW. Qualified with |
| to conduct writes to the SRAM. | |||||||||||||
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| BW | WE | |||||||||||||||||||
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| BWb | Synchronous | Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, | ||||||||||||||||||
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| BWc |
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| BWc controls DQc and DQPc, BWd controls DQd and DQPd. | ||||||||||||||||
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| BWd |
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| Input- | Write Enable Input, active LOW. Sampled on the rising edge of CLK if |
| is active LOW. This | |||||||||
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| WE | CEN | |||||||||||||||||||
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| Synchronous | signal must be asserted LOW to initiate a write sequence. | |||||||||||
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| Input- | Advance/Load Input used to advance the | |||||||||||
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| ADV/LD |
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| Synchronous | When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a | |||||||||||
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| new address can be loaded into the device for an access. After being deselected, ADV/LD should | |||||||||
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| be driven LOW in order to load a new address. | |||||||||
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| CLK | Input- | Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with |
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| CEN. | ||||||||||||||||||||
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| Clock | CLK is only recognized if CEN is active LOW. | |||||||||||
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| 1 |
| Input- | Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with | ||||||||||||||||
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| CE | ||||||||||||||||||||
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| Synchronous | CE2 and CE3 to select/deselect the device. | |||||||||||
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| CE2 | Input- | Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction | ||||||||||||||||||
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| Synchronous | with CE1 and CE3 to select/deselect the device. | |||||||||||
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| 3 |
| Input- | Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with | ||||||||||||||||
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| CE | ||||||||||||||||||||
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| Synchronous | CE1 and CE2 to select/deselect the device. | |||||||||||
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| Input- | Output Enable, active LOW. Combined with the synchronous logic block inside the device to | |||||||||||||||
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| OE | ||||||||||||||||||||
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| Asynchronous | control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. | |||||||||||
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| When deasserted HIGH, I/O pins are | |||||||||
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| during the data portion of a write sequence, during the first clock when emerging from a | |||||||||
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| deselected state and when the device has been deselected. | |||||||||
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| Input- | Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the | |||||||||||||
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| CEN | ||||||||||||||||||||
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| Synchronous | SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not | |||||||||||
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| deselect the device, CEN can be used to extend the previous cycle when required. | |||||||||
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| DQS | I/O- | Bidirectional Data I/O lines. As inputs, they feed into an | ||||||||||||||||||
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| Synchronous | by the rising edge of CLK. As outputs, they deliver the data contained in the memory location | |||||||||||
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| specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is | |||||||||
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| controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave | |||||||||
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| as outputs. When HIGH, | |||||||||
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| automatically | |||||||||
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| emerging from a deselected state, and when the device is deselected, regardless of the state of | |||||||||
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| OE. | |||||||||
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| DQPX | I/O- | Bidirectional Data Parity I/O lines. Functionally, these signals | are | identical to DQs. During write | ||||||||||||||||
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| Synchronous | sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, | |||||||||||
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| and DQPd is controlled by BWd. | |||||||||
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| MODE | Input Strap Pin | Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. | ||||||||||||||||||
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| Pulled LOW selects the linear burst order. MODE should not change states during operation. | |||||||||
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| When left floating MODE will default HIGH, to an interleaved burst order. | |||||||||
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| TDO | JTAG serial | Serial | ||||||||||||||||||
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| output |
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| Synchronous |
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| TDI | JTAG serial | Serial | ||||||||||||||||||
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| input |
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| Synchronous |
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| TMS | Test Mode | This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. | ||||||||||||||||||
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| Select |
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| Synchronous |
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| TCK | Clock input to the JTAG circuitry. | |||||||||||||||||||
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Document #: |
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| Page 6 of 27 |
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