Cypress CY7C1370DV25, CY7C1372DV25 manual Pin Definitions, Pin Name Type Pin Description

Page 6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1370DV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1372DV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

I/O Type

Pin Description

 

 

 

 

 

 

 

A0

Input-

Address Inputs used to select one of the address locations. Sampled at the rising edge of

 

 

A1

Synchronous

the CLK.

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a

Input-

Byte Write Select Inputs, active LOW. Qualified with

 

to conduct writes to the SRAM.

 

 

BW

WE

 

 

BWb

Synchronous

Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,

 

 

BWc

 

 

 

BWc controls DQc and DQPc, BWd controls DQd and DQPd.

 

 

BWd

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Write Enable Input, active LOW. Sampled on the rising edge of CLK if

 

is active LOW. This

 

 

WE

CEN

 

 

 

 

 

 

 

 

 

 

Synchronous

signal must be asserted LOW to initiate a write sequence.

 

 

 

 

 

 

 

 

 

 

Input-

Advance/Load Input used to advance the on-chip address counter or load a new address.

 

 

ADV/LD

 

 

 

 

 

 

 

 

 

 

 

Synchronous

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

 

 

 

 

 

 

 

 

 

 

 

 

 

new address can be loaded into the device for an access. After being deselected, ADV/LD should

 

 

 

 

 

 

 

 

 

 

 

 

 

be driven LOW in order to load a new address.

 

 

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with

 

 

 

 

CEN.

 

 

 

 

 

 

 

 

 

 

Clock

CLK is only recognized if CEN is active LOW.

 

 

 

1

 

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

 

 

CE

 

 

 

 

 

 

 

 

 

 

Synchronous

CE2 and CE3 to select/deselect the device.

 

 

CE2

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

 

 

 

 

 

 

 

 

 

 

Synchronous

with CE1 and CE3 to select/deselect the device.

 

 

 

3

 

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

 

 

CE

 

 

 

 

 

 

 

 

 

 

Synchronous

CE1 and CE2 to select/deselect the device.

 

 

 

 

 

 

Input-

Output Enable, active LOW. Combined with the synchronous logic block inside the device to

 

 

OE

 

 

 

 

 

 

 

 

 

 

Asynchronous

control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.

 

 

 

 

 

 

 

 

 

 

 

 

 

When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked

 

 

 

 

 

 

 

 

 

 

 

 

 

during the data portion of a write sequence, during the first clock when emerging from a

 

 

 

 

 

 

 

 

 

 

 

 

 

deselected state and when the device has been deselected.

 

 

 

 

 

 

 

 

Input-

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the

 

 

CEN

 

 

 

 

 

 

 

 

 

 

Synchronous

SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not

 

 

 

 

 

 

 

 

 

 

 

 

 

deselect the device, CEN can be used to extend the previous cycle when required.

 

 

DQS

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

 

 

 

 

 

 

 

 

 

 

Synchronous

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

 

 

 

 

 

 

 

 

 

 

 

 

 

specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is

 

 

 

 

 

 

 

 

 

 

 

 

 

controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

 

 

 

 

 

 

 

 

 

 

 

 

 

as outputs. When HIGH, DQa–DQdare placed in a three-state condition. The outputs are

 

 

 

 

 

 

 

 

 

 

 

 

 

automatically three-stated during the data portion of a write sequence, during the first clock when

 

 

 

 

 

 

 

 

 

 

 

 

 

emerging from a deselected state, and when the device is deselected, regardless of the state of

 

 

 

 

 

 

 

 

 

 

 

 

 

OE.

 

 

DQPX

I/O-

Bidirectional Data Parity I/O lines. Functionally, these signals

are

identical to DQs. During write

 

 

 

 

 

 

 

 

 

 

Synchronous

sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,

 

 

 

 

 

 

 

 

 

 

 

 

 

and DQPd is controlled by BWd.

 

 

MODE

Input Strap Pin

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

 

 

 

 

 

 

 

 

 

 

 

 

 

Pulled LOW selects the linear burst order. MODE should not change states during operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

When left floating MODE will default HIGH, to an interleaved burst order.

 

 

TDO

JTAG serial

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

 

 

 

 

 

 

 

 

 

 

output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

 

 

 

 

 

 

 

 

 

 

 

 

TDI

JTAG serial

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

 

 

 

 

 

 

 

 

 

 

input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

 

 

 

 

 

 

 

 

 

 

 

 

TMS

Test Mode

This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

 

 

 

 

 

 

 

 

 

 

Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

 

 

 

 

 

 

 

 

 

 

 

 

TCK

JTAG-Clock

Clock input to the JTAG circuitry.

 

 

 

 

 

 

 

 

 

 

Document #: 38-05558 Rev. *D

 

 

 

 

 

 

Page 6 of 27

[+] Feedback

Image 6
Contents Functional Description FeaturesLogic Block Diagram-CY7C1370DV25 512K x Cypress Semiconductor CorporationLogic Block Diagram-CY7C1372DV25 1M x Selection Guide250 MHz 200 MHz 167 MHz Unit Pin Configurations Pin Tqfp Pinout 1M ×Pin Configurations Ball BGA Pinout CY7C1370DV25 512K ×Pin Configurations Ball Fbga Pinout Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsPin Name Type Pin Description Clock input to the Jtag circuitryIntroduction Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Partial Write Cycle Description 1, 2, 3 Address Operation UsedFunction CY7C1370DV25 TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassOutput Times TAP AC Switching Characteristics Over the Operating Range9Parameter Description Min Max Unit Clock Hold Times5V TAP AC Output Load Equivalent TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Scan Register SizesInstruction Code Description Identification CodesBall BGA Boundary Scan Order 12 Bit # Ball IDBall Fbga Boundary Scan Order 12 Operating Range Electrical Characteristics Over the Operating Range15Maximum Ratings Range AmbientAC Test Loads and Waveforms Capacitance17Thermal Resistance17 PackageSwitching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSet-up Times Address A1 A2 Switching WaveformsRead/Write/Timing24, 25 DON’T CareZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information CY7C1370DV25 CY7C1372DV25 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document History