Cypress CY7C1372DV25, CY7C1370DV25 manual Ball BGA 14 x 22 x 2.4 mm

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CY7C1370DV25

CY7C1372DV25

Package Diagrams (continued)

119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

51-85115-*B

Document #: 38-05558 Rev. *D

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Contents Logic Block Diagram-CY7C1370DV25 512K x FeaturesFunctional Description Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1372DV25 1M x250 MHz 200 MHz 167 MHz Unit 1M × Pin Configurations Pin Tqfp PinoutCY7C1370DV25 512K × Pin Configurations Ball BGA PinoutPin Configurations Ball Fbga Pinout Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Clock input to the Jtag circuitryIntroduction Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Operation Used Partial Write Cycle Description 1, 2, 3Function CY7C1370DV25 TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set TAP RegistersBypass TAP TimingParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range9Output Times Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Output Load Equivalent Scan Register SizesBall BGA Boundary Scan Order 12 Identification CodesInstruction Code Description Bit # Ball IDBall Fbga Boundary Scan Order 12 Maximum Ratings Electrical Characteristics Over the Operating Range15Operating Range Range AmbientThermal Resistance17 Capacitance17AC Test Loads and Waveforms Package250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 22Set-up Times Read/Write/Timing24, 25 Switching WaveformsAddress A1 A2 DON’T CareNOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information CY7C1370DV25 CY7C1372DV25 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History ECN No Issue Date Orig. Description of Change