Cypress CY7C1370DV25 manual Logic Block Diagram-CY7C1372DV25 1M x, Selection Guide

Page 2

 

 

 

 

 

 

 

 

 

 

CY7C1370DV25

 

 

 

 

 

 

 

 

 

 

CY7C1372DV25

Logic Block Diagram-CY7C1372DV25 (1M x 18)

 

 

 

 

 

 

 

 

A0, A1, A

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

REGISTER 0

A1

D1

Q1 A1'

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MODE

 

 

A0

D0 BURST Q0 A0'

 

 

 

 

 

 

 

 

 

ADV/LD

LOGIC

 

 

 

 

 

 

 

CLK

C

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

CEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE ADDRESS

 

WRITE ADDRESS

 

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

O

 

 

 

 

 

 

 

 

 

 

U

 

U

 

 

 

 

 

 

 

 

 

 

T

 

T

 

 

ADV/LD

 

 

 

 

 

 

S

P

D

P

 

 

 

 

 

 

 

 

E

U

A

U

 

 

 

 

 

WRITE REGISTRY

 

 

 

N

T

T

T

 

 

 

 

 

 

 

MEMORY

S

R

A

B

 

 

BWa

 

 

AND DATA COHERENCY

 

WRITE

E

 

DQs

 

 

 

 

ARRAY

 

E

S

U

 

 

 

 

CONTROL LOGIC

 

DRIVERS

A

G

DQPa

 

 

 

 

 

 

T

F

 

BWb

 

 

 

 

 

 

M

I

E

F

DQPb

 

 

 

 

 

 

 

 

P

S

E

E

 

 

 

 

 

 

 

 

T

 

 

 

 

 

 

 

 

 

S

R

R

 

 

 

 

 

 

 

 

 

 

E

I

S

 

 

WE

 

 

 

 

 

 

 

R

N

 

 

 

 

 

 

 

 

 

 

S

 

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

 

 

E

 

E

 

 

 

 

 

 

 

 

INPUT

E

 

INPUT

E

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 0

 

 

OE

 

READ LOGIC

 

 

 

 

 

 

 

 

 

CE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

 

CE3

 

 

 

 

 

 

 

 

 

 

 

 

ZZ

 

Sleep

 

 

 

 

 

 

 

 

 

 

 

Control

 

 

 

 

 

 

 

 

Selection Guide

 

250 MHz

200 MHz

167 MHz

Unit

Maximum Access Time

2.6

3.0

3.4

ns

Maximum Operating Current

350

300

275

mA

Maximum CMOS Standby Current

70

70

70

mA

Document #: 38-05558 Rev. *D

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1370DV25 512K x Cypress Semiconductor Corporation250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1372DV25 1M xSelection Guide Pin Configurations Pin Tqfp Pinout 1M ×Pin Configurations Ball BGA Pinout CY7C1370DV25 512K ×Pin Configurations Ball Fbga Pinout Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsPin Name Type Pin Description Clock input to the Jtag circuitryIntroduction ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1370DV25 Partial Write Cycle Description 1, 2, 3Address Operation Used Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Registers TAP Instruction SetTAP Timing BypassOutput Times TAP AC Switching Characteristics Over the Operating Range9Parameter Description Min Max Unit Clock Hold Times5V TAP AC Output Load Equivalent TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Scan Register SizesInstruction Code Description Identification CodesBall BGA Boundary Scan Order 12 Bit # Ball IDBall Fbga Boundary Scan Order 12 Operating Range Electrical Characteristics Over the Operating Range15Maximum Ratings Range AmbientAC Test Loads and Waveforms Capacitance17Thermal Resistance17 PackageSet-up Times Switching Characteristics Over the Operating Range 22250 200 167 Parameter Description Unit Min Max Address A1 A2 Switching WaveformsRead/Write/Timing24, 25 DON’T CareZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information CY7C1370DV25 CY7C1372DV25 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document History
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