Cypress CY7C1372DV25 manual Pin Configurations Ball BGA Pinout, CY7C1370DV25 512K ×

Page 4

CY7C1370DV25

CY7C1372DV25

Pin Configurations (continued)

119-Ball BGA Pinout

CY7C1370DV25 (512K × 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

A

VDDQ

B

NC/576M

CE2

A

ADV/LD

A

CE3

NC

C

NC/1G

A

A

VDD

A

A

NC

D

DQc

DQPc

VSS

NC

VSS

DQPb

DQb

E

DQc

DQc

VSS

CE

1

VSS

DQb

DQb

F

VDDQ

DQc

VSS

VSS

DQb

VDDQ

OE

G

DQc

DQc

c

A

b

DQb

DQb

BW

BW

H

DQc

DQc

VSS

VSS

DQb

DQb

WE

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQd

DQd

VSS

CLK

VSS

DQa

DQa

L

DQd

DQd

d

NC

a

DQa

DQa

BW

BW

M

VDDQ

DQd

VSS

VSS

DQa

VDDQ

CEN

N

DQd

DQd

VSS

A1

VSS

DQa

DQa

P

DQd

DQPd

VSS

A0

VSS

DQPa

DQa

R

NC/144M

A

MODE

VDD

NC

A

NC/288M

T

NC

NC/72M

A

A

A

NC/36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1372DV25 (1M x 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

A

VDDQ

B

NC/576M

CE2

A

A

3

NC

ADV/LD

CE

C

NC/1G

A

A

VDD

A

A

NC

D

DQb

NC

VSS

NC

VSS

DQPa

NC

E

NC

DQb

VSS

1

VSS

NC

DQa

CE

F

VDDQ

NC

VSS

VSS

DQa

VDDQ

OE

G

NC

DQb

b

A

NC

NC

DQa

BW

H

DQb

NC

VSS

VSS

DQa

NC

WE

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQb

VSS

CLK

VSS

NC

DQa

L

DQb

NC

NC

NC

DQa

NC

BW

a

M

VDDQ

DQb

VSS

VSS

NC

VDDQ

CEN

N

DQb

NC

VSS

A1

VSS

DQa

NC

P

NC

DQPb

VSS

A0

VSS

NC

DQa

R

NC/144M

A

MODE

VDD

NC

A

NC/288M

T

NC/72M

A

A

NC/36M

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document #: 38-05558 Rev. *D

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Contents Features Logic Block Diagram-CY7C1370DV25 512K xFunctional Description Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1372DV25 1M x250 MHz 200 MHz 167 MHz Unit Pin Configurations Pin Tqfp Pinout 1M ×Pin Configurations Ball BGA Pinout CY7C1370DV25 512K ×Pin Configurations Ball Fbga Pinout Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with Clock input to the Jtag circuitryIntroduction Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Operation Used Partial Write Cycle Description 1, 2, 3Function CY7C1370DV25 TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassTAP AC Switching Characteristics Over the Operating Range9 Parameter Description Min Max Unit ClockOutput Times Hold TimesTAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order 12Instruction Code Description Bit # Ball IDBall Fbga Boundary Scan Order 12 Electrical Characteristics Over the Operating Range15 Maximum RatingsOperating Range Range AmbientCapacitance17 Thermal Resistance17AC Test Loads and Waveforms Package250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 22Set-up Times Switching Waveforms Read/Write/Timing24, 25Address A1 A2 DON’T CareZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information CY7C1370DV25 CY7C1372DV25 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document History