Cypress CY7C1370DV25, CY7C1372DV25 manual Ball Fbga Boundary Scan Order 12

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					CY7C1370DV25
					CY7C1372DV25
					CY7C1372DV25


165-Ball FBGA Boundary Scan Order [12, 14]
Bit #	Ball ID	Bit #	Ball ID	Bit #		Ball ID

1	N6	31	D10	61		G1

2	N7	32	C11	62		D2

3	N10	33	A11	63		E2

4	P11	34	B11	64		F2

5	P8	35	A10	65		G2

6	R8	36	B10	66		H1

7	R9	37	A9	67		H3

8	P9	38	B9	68		J1

9	P10	39	C10	69		K1

10	R10	40	A8	70		L1

11	R11	41	B8	71		M1

12	H11	42	A7	72		J2

13	N11	43	B7	73		K2

14	M11	44	B6	74		L2

15	L11	45	A6	75		M2

16	K11	46	B5	76		N1

17	J11	47	A5	77		N2

18	M10	48	A4	78		P1

19	L10	49	B4	79		R1

20	K10	50	B3	80		R2

21	J10	51	A3	81		P3

22	H9	52	A2	82		R3

23	H10	53	B2	83		P2

24	G11	54	C2	84		R4

25	F11	55	B1	85		P4

26	E11	56	A1	86		N5

27	D11	57	C1	87		P6

28	G10	58	D1	88		R6

29	F10	59	E1	89		Internal

30	E10	60	F1

Note:

14. Bit# 89 is pre-set HIGH.

Document #: 38-05558 Rev. *D

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Contents Features Logic Block Diagram-CY7C1370DV25 512K xFunctional Description Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1372DV25 1M x250 MHz 200 MHz 167 MHz Unit Pin Configurations Pin Tqfp Pinout 1M ×Pin Configurations Ball BGA Pinout CY7C1370DV25 512K ×Pin Configurations Ball Fbga Pinout Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with Clock input to the Jtag circuitryIntroduction Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Operation Used Partial Write Cycle Description 1, 2, 3Function CY7C1370DV25 TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassTAP AC Switching Characteristics Over the Operating Range9 Parameter Description Min Max Unit ClockOutput Times Hold TimesTAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order 12Instruction Code Description Bit # Ball IDBall Fbga Boundary Scan Order 12 Electrical Characteristics Over the Operating Range15 Maximum RatingsOperating Range Range AmbientCapacitance17 Thermal Resistance17AC Test Loads and Waveforms Package250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 22Set-up Times Switching Waveforms Read/Write/Timing24, 25Address A1 A2 DON’T CareZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information CY7C1370DV25 CY7C1372DV25 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1372DV25

165-Ball FBGA Boundary Scan Order [12, 14]

Bit #