CY7C1370DV25
CY7C1372DV25
Document History Page
Document Title: CY7C1370DV25/CY7C1372DV25
Pipelined SRAM with NoBL™ Architecture
Document Number:
REV. | ECN No. | Issue Date | Orig. of | Description of Change |
Change | ||||
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** | 254509 | See ECN | RKF | New data sheet |
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*A | 288531 | See ECN | SYT | Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for |
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| Removed 225 Mhz Speed Bin |
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| Added |
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| package |
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| Added comment of |
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| Information |
*B | 326078 | See ECN | PCI | Address expansion pins/balls in the pinouts for all packages are modified as |
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| per JEDEC standard |
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| Added description on EXTEST Output Bus |
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| Changed description on the Tap Instruction Set Overview and Extest |
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| Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and |
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| 4.08 °C/W respectively |
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| Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 |
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| °C/W respectively |
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| Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and |
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| 4.0 °C/W respectively |
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| Modified VOL, VOH test conditions |
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| Removed comment of |
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| Ordering Information |
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| Updated Ordering Information Table |
*C | 418125 | See ECN | NXR | Converted from Preliminary to Final |
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| Changed address of Cypress Semiconductor Corporation on Page# 1 from |
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| “3901 North First Street” to “198 Champion Court” |
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| Changed the description of IX from Input Load Current to Input Leakage |
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| Current on page# 18 |
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| Changed the IX current values of MODE on page # 18 from |
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| to |
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| Changed the IX current values of ZZ on page # 18 from |
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| to |
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| Changed VIH < VDD to VIH < VDDon page # 18 |
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| Updated Ordering Information Table |
*D | 475677 | See ECN | VKN | Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. |
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| Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP |
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| AC Switching Characteristics table. |
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| Updated the Ordering Information table. |
Document #: | Page 27 of 27 |
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