Cypress CY7C1370DV25, CY7C1372DV25 manual TAP Timing, Bypass

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CY7C1370DV25

CY7C1372DV25

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #85 (for 119-BGA package) or bit #89 (for 165-fBGA package). When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the

current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1 2

Test Clock

(TCK)tTH

tTMSS tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3

4

5

6

tTL tCYC

tTDOV

tTDOX

Test Data-Out (TDO)

DON’T CARE

UNDEFINED

Document #: 38-05558 Rev. *D

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Contents Features Logic Block Diagram-CY7C1370DV25 512K xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1372DV25 1M x Selection Guide250 MHz 200 MHz 167 MHz Unit Pin Configurations Pin Tqfp Pinout 1M ×Pin Configurations Ball BGA Pinout CY7C1370DV25 512K ×Pin Configurations Ball Fbga Pinout Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with Clock input to the Jtag circuitryIntroduction Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Partial Write Cycle Description 1, 2, 3 Address Operation UsedFunction CY7C1370DV25 TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassTAP AC Switching Characteristics Over the Operating Range9 Parameter Description Min Max Unit ClockOutput Times Hold TimesTAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order 12Instruction Code Description Bit # Ball IDBall Fbga Boundary Scan Order 12 Electrical Characteristics Over the Operating Range15 Maximum RatingsOperating Range Range AmbientCapacitance17 Thermal Resistance17AC Test Loads and Waveforms PackageSwitching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSet-up Times Switching Waveforms Read/Write/Timing24, 25Address A1 A2 DON’T CareZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information CY7C1370DV25 CY7C1372DV25 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document History
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