Cypress CY7C1372DV25, CY7C1370DV25 manual NOP,STALL and Deselect Cycles24, 25, ZZ Mode Timing28

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CY7C1370DV25

CY7C1372DV25

Switching Waveforms (continued)

NOP,STALL and DESELECT Cycles[24, 25, 27]

1

2

3

4

5

6

7

8

9

10

CLK

CEN

CE

ADV/LD

WE

BWx

ADDRESS A1 A2 A3 A4 A5

tCHZ

Data

In-Out (DQ)

WRITE

D(A1)

READ Q(A2)

STALL

D(A1)

READ

Q(A3)

Q(A2)	Q(A3)		D(A4)	Q(A5)
WRITE	STALL	NOP	READ	DESELECT CONTINUE
D(A4)			Q(A5)	DESELECT
DON’T CARE		UNDEFINED

ZZ Mode Timing[28, 29]

CLK

ZZ

ISUPPLY

ALL INPUTS (except ZZ)

Outputs (Q)

tZZ

t ZZI

I DDZZ

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

Notes:

27.The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle

28.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

29.I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05558 Rev. *D

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Contents Logic Block Diagram-CY7C1370DV25 512K x FeaturesFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1372DV25 1M x Selection Guide250 MHz 200 MHz 167 MHz Unit 1M × Pin Configurations Pin Tqfp PinoutCY7C1370DV25 512K × Pin Configurations Ball BGA PinoutPin Configurations Ball Fbga Pinout Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Clock input to the Jtag circuitryIntroduction Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Partial Write Cycle Description 1, 2, 3 Address Operation UsedFunction CY7C1370DV25 TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set TAP RegistersBypass TAP TimingParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range9Output Times Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Output Load Equivalent Scan Register SizesBall BGA Boundary Scan Order 12 Identification CodesInstruction Code Description Bit # Ball IDBall Fbga Boundary Scan Order 12 Maximum Ratings Electrical Characteristics Over the Operating Range15Operating Range Range AmbientThermal Resistance17 Capacitance17AC Test Loads and Waveforms PackageSwitching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSet-up Times Read/Write/Timing24, 25 Switching WaveformsAddress A1 A2 DON’T CareNOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information CY7C1370DV25 CY7C1372DV25 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History ECN No Issue Date Orig. Description of Change